• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.5
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• pp.24-29
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• 1976

In the phase locked AM signal detection, phase locked loop is used to extract a synchronous carrier from an input AM signal. Under the assumption that input noise is white Gaussian and free-running frequency of voltage controlled oscillator is the same that of an input carrier, operational behaviours of phase locked loop is analyzed and signal to noise ratio of the detection is derived quentitatively. The results show that the phase locked AM signal detection method offers a higher degree of noise mmunity than conventional AM signal detections.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.9
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• pp.461-466
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• 1999

The switched reluctance motor (SRM) would have torque ripple if not operated with an MMF waveform specified for switching angle and phase voltage. This paper describes the robustic control scheme that permits the phase torque to be flat by PLL(Phase Locked Loop) controller. In this control scheme, the locked phase signal of PLL controls the switching dwell angle and it's loop filter signal controls the switching voltage adaptively. Experimental results show that stable dynamic performance is obtained for torque and speed together with low torque ripple on the operation of variable loads.

• Journal of Power Electronics
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• v.16 no.1
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• pp.310-318
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• 2016

This paper presents a new orthogonal signals generator (OSG) with DC Offset rejection for implementing a phase locked loop (PLL) in single-phase grid-connected power systems. An adaptive filter (AF) based on the least mean square (LMS) algorithm is used to constitute the OSG in this study. The DC offset in the measured grid voltage signal can be significantly rejected in the developed OSG technique. This generates two pure orthogonal signals that are free from the DC offset. As a result, the DC offset rejection performance of the presented single-phase phase locked loop (SPLL) can be enhanced. A mathematical model of the developed OSG and the principle of the adaptive filter based SPLL (AF-SPLL) are presented in detail. Finally, simulation and experimental results demonstrate the feasibility of the proposed AF-SPLL.

• Journal of Power Electronics
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• v.14 no.6
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• pp.1334-1344
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• 2014

A novel single phase Phase-Locked Loop (PLL) is proposed in this paper to accurately and rapidly estimate the instantaneous phase angle of a grid. A conjugate rotating vector pair is proposed and defined to synthesize the single phase signal in the stationary reference frame. With this concept, the proposed PLL innovatively sets one phase input of the PARK transformation to a constant zero. By means of a proper cancellation, a zero steady state phase angle estimation error can be achieved, even under magnitude and frequency variations. The proposed PLL structure is presented together with guidelines for parameters adjustment. The performance of the proposed PLL is verified by comprehensive experiments. Satisfactory phase angle estimation can be achieved within one input signal cycle, and the estimation error can be totally eliminated in four input cycles for the most severe conditions.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.203-204
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• 2006

We present and demonstrate a novel method of alternate-phase return-to-zero (RZ) signal generation and pulse-amplitude equalization simultaneously in a rational harmonic mode-locked fiber ring laser, using a dual-drive Mach-Zehnder (MZ) modulator. By adjusting the voltages applied to both arms of the modulator, the rational harmonic mode-locked pulse trains are equalized in their amplitudes. In addition to that, the amplitude-equalized pulse trains multiplying the repetition rate at ${\sim}10\;GHz$ have alternate $\pi$ phase difference between adjacent pulses. The alternate-phase RZ signal generated by the proposed method enhances transmission performance through the single-mode fiber (SMF) links without dispersion compensation.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.7
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• pp.2891-2903
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• 2020

Phase-generated carrier (PGC) demodulation algorithm is the main demodulation methods in Fiber-optic interferometric sensors (FOISs). The conventional PGC demodulation algorithms are influenced by the carrier phase delay between the interference signal and the carrier signal. In this paper, an automatic carrier phase delay synchronization (CPDS) algorithm based on orthogonal phase-locked technique is proposed. The proposed algorithm can calculate the carrier phase delay value. Then the carrier phase delay can be compensated by adjusting the initial phase of the fundamental carrier and the second-harmonic carrier. The simulation results demonstrate the influence of the carrier phase delay on the demodulation performance. PGC-Arctan demodulation system based on CPDS algorithm is implemented on SoC. The experimental results show that the proposed algorithm is able to obtain and eliminate the carrier phase delay. In comparison to the conventional demodulation algorithm, the signal-to-noise and distortion ratio (SINAD) of the proposed algorithm increases 55.99dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.5
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• pp.949-954
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• 2007

In this work, temperature stable frequency-to-voltage converter is proposed. In FVC circuit input frequency is converted into output voltage signal. A FLL is similar to PLL in the way that it generates an output signal which tracks an input reference signal. A PLL is built on a phase detector, a charge pump, and a low pass filter. However, FLL does not require the use of the phase detector, the charge pump and low pass filter. The FVC is designed by using $0.25{\mu}m$ CMOS process technology. From simulation results, the variation of output voltage is less than ${\pm}2%$ in the temperature range $0^{\circ}C\;to\;75^{\circ}C$ when the input frequency is from 70MHz to 140MHz.

• Korean Journal of Optics and Photonics
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• v.10 no.6
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• pp.507-511
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• 1999

A 10 GHz timing extracted signal which is phase-locked to a 10 Gbit/s mode-locked optical fiber laser pulse train is obtained using a tour-wave-mixing signal in semiconductor optical amplifier. The phase-locked loop wm, demonstrated ~Llccessful1y over 8 hours and found to have the lock-in frequency range of 30 KHz. 0 KHz.

• Journal of Power Electronics
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• v.13 no.5
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• pp.884-895
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• 2013

In this paper, the Fourier-based PLL (Phase-locked Loop) is introduced with a new structure, capable of selective harmonic detection in single and three-phase systems. The application of the FB-PLL to harmonic detection is discussed and a new model applicable to three-phase systems is introduced. An analysis of the convergence of the FB-PLL based on a linear model is presented. Simulation and experimental results are included for performance analysis and to support the theoretical development. The decomposition of an input signal in its harmonic components using the Fourier theory is based on previous knowledge of the signal fundamental frequency, which cannot be easily implemented with input signals with varying frequencies or subjected to phase-angle jumps. In this scenario, the main contribution of this paper is the association of a phase-locked loop system, with a harmonic decomposition and reconstruction method, based on the well-established Fourier theory, to allow for the tracking of the fundamental component and desired harmonics from distorted input signals with a varying frequency, amplitude and phase-angle. The application of the proposed technique in three-phase systems is supported by results obtained under unbalanced and voltage sag conditions.

• Journal of electromagnetic engineering and science
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• v.17 no.2
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• pp.98-104
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• 2017

This work describes the development and comparison of two phase-locked loops (PLLs) based on a 65-nm CMOS technology. The PLLs incorporate two different topologies for the output voltage-controlled oscillator (VCO): LC cross-coupled and differential Colpitts. The measured locking ranges of the LC cross-coupled VCO-based phase-locked loop (PLL1) and the Colpitts VCO-based phase-locked loop (PLL2) are 119.84-122.61 GHz and 126.53-129.29 GHz, respectively. Th e output powers of PLL1 and PLL2 are -8.6 dBm and -10.5 dBm with DC power consumptions of 127.3 mW and 142.8 mW, respectively. Th e measured phase noise of PLL1 is -59.2 at 10 kHz offset and -104.5 at 10 MHz offset, and the phase noise of PLL2 is -60.9 dBc/Hz at 10 kHz offset and -104.4 dBc/Hz at 10 MHz offset. The chip sizes are $1,080{\mu}m{\times}760{\mu}m$ (PLL1) and $1,100{\mu}m{\times}800{\mu}m$ (PLL2), including the probing pads.