• 한국전기전자재료학회논문지
• /
• 제13권1호
• /
• pp.13-20
• /
• 2000

In this paper, we demonstrated an analytical description method of forward votage drop and reverse leakage current of the junction barrier controlled schottky rectifier with linearly graded junction and abrupt junction models. In this case, the vertical depths of device are 1[${\mu}{\textrm}{m}$] and 2[${\mu}{\textrm}{m}$], respectively. Through ion implantation and annealing process, we obtain the data of lateral and depth from implanted 2-dimensional profiles. Also we applied these data to models that indicate the change of depletion each on linearly-graded and abrupt juction as the forward and revers bias. After applied depletion changes to electric characteristics of JBS rectifiers, we calculated the forward I-V, the reverse leakage current and temperatures vs. power dissipations according to each junction. When we compared the rectifier with calculated and measured data, from the calculated results, forward votage drop with linearly graded junction is lower than that of abrupt junction and reverse leakage current with linearly graded junction is lower(≒1$\times$10\ulcorner times) than that of abrupt junction. Also, the power dissipations according to different juction depth(1[${\mu}{\textrm}{m}$], 2[${\mu}{\textrm}{m}$]) of device are calculated. Seeing the calculated results, we confirmed it from analytic model that the rectifier with linearly graded junction retained a low power dissipation up to 600[$^{\circ}C$] in comparison with the rectifier with abrupt junction.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2000년도 하계학술대회 논문집
• /
• pp.63-66
• /
• 2000

In this paper, we present the simulation of the heterojunction bipolar transistor with different Emitter-Base junction structures. Our simulation results include effect of setback and graded layer. We prove the emitter efficiency's improvement through setback and graded layer. In 1995, the analytical equations of electric field, electrostatic potential, and junction capacitance for abrupt and linearly graded heterojunctions with or without a setback layer was derived. But setback layer and linearly graded layer's recombination current was considered numerically. Later, recombination current model included setback layer and graded layer will be proposed. New recombination current model also wile include abrupt heterojunction's recombination current model. In this paper, the material parameters of the heterojunction bipolar transistor with different Emitter-Base junction structures is introduced.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2000년도 하계학술대회 논문집
• /
• pp.67-70
• /
• 2000

In this paper, all SCR recombination currents including setback and graded layer's recombination currents are analytically introduced for the first time. Different emitter-base structures are tested to prove the validity of the model. In 1995, the analytical equations of electric field, electrostatic potential, and junction capacitance for abrupt and linearly graded heterojunctions with or without a setback layer was derived. But setback layer and linearly graded layer's recombination current was considered numerically. In this paper, recombination current model included setback layer and graded layer is proposed. New recombination current model also includes abrupt heterojunction's recombination current model. In this paper, new recombination current model analytically explains effects of setback layer and graded layer.

• 전자공학회논문지
• /
• 제50권7호
• /
• pp.109-114
• /
• 2013

전력 MOSFET(산화물-반도체 전위 효과 트랜지스터)는 BLDC 모터와 전력 모듈 등에 광범위하게 사용하고 있다. 기존 전력 MOSFET 구조는 온-저항과 항복전압사이에 절충(tradeoff)이 필요하다. 이러한 절충을 하지 않고 최적화를 하기위해 비균일 초접합 트랜치 MOSFET 를 설계하는데 동일한 항복전압에서 균일 초접합 트랜치 MOSFET보다 낮은 온-저항을 갖도록한다. 이를 위해 드리프트 영역에서 우수한 전기장 분포를 달성하기 위하여 선형구조의 도핑 프로파일을 제안하고, 단위 셀 설계, 도핑농도의 특성분석, 전위분포를 SILVACO TCAD 2D인 Atlas 소자 소프트웨어를 사용하여 시뮬에이션을 수행하였다. 결과로 100V 급 MOSFET에서 비균일 초접합 트랜치 MOSFET가 균일 초접합 트랜치 MOSFET보다 온-저항에서 우수한 특성을 보여주고 있다.

• 전자공학회논문지A
• /
• 제31A권2호
• /
• pp.88-93
• /
• 1994

We fabricated a large-scale photovoltaic device for detecting-3-5$\mu$m IR, by forming of n$^{+}$-p junction in the $Hg_{1-x}Cd_{x}$Te (MCT) layer which was grown by LPE on CdTe substrate. The composition x of the MCT epitaxial layer was 0.295 and the hole concentration was 1.3${\times}10^{13}/cm^{4}$. The n$^{+}$-p junction was formed by B+ implantation at 100 keV with a does 3${\times}10^{11}/cm^{2}. The n$^{+}$ region has a circular shape with 2.68mm diameter. The vacuum-evaporated ZnS with resistivity of 2${\times}10^{4}{\Omega}$cm is used as an insulating layer over the epitaxial layer. ZnS plays the role of the anti-reflection coating transmitting more than 90% of 3~5$\mu$m IR. For ohmic contacts, gole was used for p-MCT and indium was used for n$^{+}$-MCT. The fabrication took 5 photolithographic masks and all the processing temperatures of the MCT wafer were below 90$^{\circ}C$. The R,A of the fabricated devices was 7500${\Omega}cm^{2}$. The carrier lifetime of the devices was estimated 2.5ns. The junction was linearly-graded and the concentration slope was measured to be 1.7${\times}10^{17}/{\mu}m$. the normalized detectivity in 3~5$\mu$m IR was 1${\times}10^{11}cmHz^{12}$/W, which is sufficient for real application.