• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.211.1-211.1
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• 2014

Recently, the scaling of conventional planar NAND flash devices is facing its limits by decreasing numbers of electron stored in the floating gate and increasing difficulties in patterning. Three-dimensional vertical NAND devices have been proposed to overcome these issues. Atomic layer deposition (ALD) is the most promising method to deposit charge trap layer of vertical NAND devices, SiN, with excellent quality due to not only its self-limiting growth characteristics but also low process temperature. ALD of silicon nitride were studied using NH3 and silicon chloride precursors, such as SiCl4[1], SiH2Cl2[2], Si2Cl6[3], and Si3Cl8. However, the reaction mechanism of ALD silicon nitride process was rarely reported. In the present study, we used density functional theory (DFT) method to calculate the reaction of silicon chloride precursors with a silicon nitride surface. DFT is a quantum mechanical modeling method to investigate the electronic structure of many-body systems, in particular atoms, molecules, and the condensed phases. The bond dissociation energy of each precursor was calculated and compared with each other. The different reactivities of silicon chlorides precursors were discussed using the calculated results.

• Proceedings of the KIEE Conference
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• 2000.11c
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• pp.455-457
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• 2000

In this work the electrical characteristics of organic TFTs with the semiconductor-insulator interfaces, where the gate dielectrics were treated by the two methods which are the deposition of Octadecyltrichlorosilane (OTS) on the insulator and rubbing the insulator surface. Pentacene is used as an active semiconducting layer. The semiconductor layer of pentacene was thermally evaporated in vacuum at a pressure of about $2{\times}10^{-7}$ Torr and at a deposition rate of $0.3{\AA}/sec$. Aluminum and gold were used for the gate and source/drain electrodes. OTS is used as a self-alignment layer between $SiO_2$ and pentacene. The gate dielectric surface was rubbed before pentacene is deposited on the insulator. In order to confirm the changes of the surface morphology the atomic force microscopy (AFM) was utilized. The characteristics of the fabricated TFTs are measured to clarify the effects of the surface treatment.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.12
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• pp.1091-1098
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• 1998

Thermal stability of the electroless deposited Cu thin film was investigated. Cu/TaN/Si multilayer was fabricated by electroless-depositing Cu thin layer on TaN diffusion barrier layer which was deposited by MOCVD on the Si substrate, and was annealed in $H_2$ ambient to investigate the microstructure of Cu film with a post heat-treatment. Cu thin film with good adhesion was successfully deposited on the surface of the TaN film by electroless deposition with a proper activation treatment and solution control. Microstructural property of the electroless-deposited Cu layer was improved by a post-annealing in the reduced atmosphere of $H_2$ gas up to $600^{\circ}C$. Thermal stability of Cu/TaN/Si system was maintained up to $600^{\circ}C$ annealing temperature, but the intermediate compounds of Cu-Si were formed above $650^{\circ}C$ because Cu element passed through the TaN layer. On the other hand, thermal stability of the Cu/TaN/Si system in Ar ambient was maintained below $550^{\circ}C$ annealing temperature due to the minimal impurity of $O_2$ in Ar gas.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.20-23
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• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing(CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical polishing(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commercial slurries pads, and post-CMP cleaning alternatives are discuss, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper deposition is a mature process from a historical point of view, but a very young process from a CMP perspective. While copper electro deposition has been used and studied for decades, its application to Cu damascene wafer processing is only now gaining complete acceptance in the semiconductor industry. The polishing mechanism of Cu-CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper passivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.61-62
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• 2006

In this paper, it was demonstrated that organic thin- film transistors (OTFTs) were fabricated with the organic adhesion layer between an organic semiconductor and a gate insulator by vapor deposition polymerization (VDP) processing. In order to form polymeric film as an adhesion layer, VDP process was also introduced instead of spin-coating process, where polymeric film was co-deposited by high-vacuum thermal evaporation from 6FDA and ODA followed by curing. The saturated slop in the saturation region and the subthreshold nonlinearity in the triode region were c1early observed in the electrical output characteristics in our organic thin film transistors using the staggered-inverted top-contact structure. Field effect mobility, threshold voltage, and on-off current ratio in 15-nm-thick organic adhesion layer were about $0.5\;cm^2/Vs$, -1 V, and $10^6$, respectively. We also demonstrated that threshold voltage depends strongly on the delay time when a gate voltage has been applied to bias stress.

• Current Optics and Photonics
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• v.2 no.2
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• pp.153-164
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• 2018

In semiconductor manufacturing, critical dimensions indicate the features of patterns formed by the semiconductor process. The purpose of measuring critical dimensions is to confirm whether patterns are made as intended. The deposition process for an organic light emitting diode (OLED) forms a luminous organic layer on the thin-film transistor electrode. The position of this organic layer greatly affects the luminescent performance of an OLED. Thus, a system for measuring the position of the organic layer from outside of the vacuum chamber in real-time is desired for monitoring the deposition process. Typically, imaging from large stand-off distances results in low spatial resolution because of diffraction blur, and it is difficult to attain an adequate industrial-level measurement. The proposed method offers a new superresolution single-image using a conversion formula between two different optical systems obtained by a deep learning technique. This formula converts an image measured at long distance and with low-resolution optics into one image as if it were measured with high-resolution optics. The performance of this method is evaluated with various samples in terms of spatial resolution and measurement performance.

• Archives of Metallurgy and Materials
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• v.64 no.2
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• pp.607-611
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• 2019

Thermal/cold spray deposition were used for additive manufacture of oxide dispersion strengthened (ODS) steel layers. Mechanically alloyed F/M ODS steel powders (Fe(bal.)-10Cr-1Mo-0.25Ti-0.35Y2O3 in wt.%) were sprayed by a high velocity oxygen fuel (HVOF) and cold spray methods. HVOF, as a thermal method, was used for manufacturing a 1 mm-thick ODS steel layer with a ~95% density. The source to objective distance (SOD) and feeding rate were controlled to achieve sound manufacturing. Y₂Ti₂O₇ nano-particles were preserved in the HVOF sprayed layer; however, unexpected Cr₂O₃ phases were frequently observed at the boundary area of the powders. A cold spray was used for manufacturing the Cr₂O₃-free layer and showed great feasibility. The density and yield of the cold spray were roughly 80% and 45%, respectively. The softening of ODS powders before the cold spray was conducted using a tube furnace of up to 1200℃. Microstructural characteristics of the cold sprayed layer were investigated by electron back-scattered diffraction (EBSD), the uniformity of deformation amount inside powders was observed.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.196.1-196.1
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• 2016

TCO(Transparent Conducting Oxide) on flat glass is used in thin-film photovoltaic cell, flat-panel display. Nowadays, Corning(R) Willow Glass(R), known as flexible substrate, has attracted much attention due to its many advantages such as reliable roll-to-roll glass processing, high-quality flexible electronic devices, high temperature process. Also, it can be an alternative to flexible polymer substrates which have their poor stability and degradation of electrical and optical qualities. For application on willow glass, the flexibility, electrical, optical properties can be greatly influenced by the TCO thin film thickness due to the inherent characterization of thin film in nanoscale. It can be expected that while thick TCO layer causes poor transparency, its sheet resistance become low. Also, rarely reports were focusing on the influence of flexible properties by varying TCO thickness on flexible glass. Therefore, it is very important to optimize TCO thickness on flexible Willow glass. In this study, Ti-ZnO thin films, with different thickness varied from 0 nm to 50 nm, were deposited on the flexible willow glass by atomic layer deposition (ALD). The flexible, electrical and optical properties were investigated, respectively. Also, these properties of Ti-doped ZnO thin films were compared with un-doped ZnO thin film. Based on the results, when Ti-ZnO thin films thickness increased, resistivity decreased and then saturated; transmittance decreased. The Figure of Merit (FoM) and flexibility was the highest when Ti-ZnO thickness was 40nm. The flexible, electrical and optical properties of Ti-ZnO thin films were better than ZnO thin film at the same thickness.

• Progress in Superconductivity and Cryogenics
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• v.13 no.1
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• pp.6-11
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• 2011

The $BaHfO_3$ (BHO) buffer layer on the IBAD MgO template was turned to be effective for a successful fabrication of $GdBa_2Cu_3O_{7-{\delta}}$ (GdBCO) films with high critical current density ($J_c$). Both the BHO buffer layers and GdBCO films were prepared by pulsed laser deposition (PLD). The effects of the PLD conditions, including substrate temperature ($T_s$), oxygen partial pressure ($PO_2$), and deposition time on the in-plane texture, surface roughness, and microstructures of the BHO buffer layers on the IBAD MgO template were systematically studied for processing optimization. The c-axis oriented growth of BHO layers was insensitive to the deposition temperature and the film thickness, while the in-plane texture and surface roughness of those were improved with increasing $T_s$ from 700 to $800^{\circ}C$. On the optimally processed BHO buffer layer, the highest $J_c$ value (77 K, self-field) of 3.68 $MA/cm^2$ could be obtained from GdBCO film deposited at $780^{\circ}C$, representing that BHO is a strong candidate for the buffer layer on the IBAD MgO template.

• Journal of the Korean Vacuum Society
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• v.2 no.4
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• pp.439-454
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• 1993

The phase sequence of codeposited Co-Si alloy and Co/si multilayer thin film was investigated by differential scanning calormetry(DSC) and X-ray diffraction (XRD) analysis, The phase sequence in codeposition and codeposited amorphous Co-Si alloy thin film were CoSilongrightarrow Co2Si and those in Co/Si multilayer thin film were CoSilongrightarrowCo2Silongrightarrow and CoSilongrightarrowCo2Si longrightarrowCoSilongrightarrowCoSi2 with the atomic concentration ration of Co to Si layer being 2:1 and 1:2 respectively. The observed phase sequence was analyzed by the effectvie heat of formatin . The phase determining factor (PDF) considering structural facotr in addition to the effectvie heat of formation was used to explain the difference in the first crystalline phase between codeposition, codeposited amorphous Co-Si alloy thin film and Co/Si multilayer thin film. The crystallinity of Co-silicide deposited by multitarget bias cosputter deposition (MBCD) wasinvestigated as a funcion of deposition temperature and substrate bias voltage by transmission electron microscopy (TEM) and epitaxial CoSi2 layer was grown at $200^{\circ}C$ . Parameters, Ear, $\alpha$(As), were calculate dto quantitatively explain the low temperature epitaxial grpwth of CoSi2 layer. The phase sequence and crystallinity had a stronger dependence on the substrate bias voltage than on the deposition temperature due to the collisional daxcade mixing, in-situ cleannin g, and increase in the number of nucleation sites by ion bombardment of growing surface.