• 한국정보디스플레이학회:학술대회논문집
• /
• 2004.08a
• /
• pp.475-478
• /
• 2004

In this paper, we describe a powerful solution for efficient LED wall calibration through the use of a quality 2D-luminance meter : the MURATest and a dedicated applicative software. The intended calibration allows adjusting individually the intensity of each LED so as to obtain a good uniformity on the module. Furthermore the intensity of each module can be adjusted one to the others so as to obtain a good uniformity on a complete display and maintain it even after module exchange for display maintenance needs.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2000.01a
• /
• pp.57-58
• /
• 2000

we have grown vertically aligned carbon nanotubes on a large area of Co-Ni codeposited Si substrates by thermal chemical vapor deposition using $C_2H_2$ gas. The carbon nanotubes grown by the thermal chemical vapor deposition are multi-wall structure, and the wall suface of nanotubes is covered with defective carbons or carbonaceous particles. The carbon nanotubes range from 50 to 120 nm in diameter and about 130 ${\mu}m$ in length at $950\;^{\circ}C$. Steric hindrance between nanotubes at an initial stage of the growth forces nanotubes to align vertically. The turn-on voltage was about 0.8 $V/{\mu}m$ with a current density of 0.1 ${\mu}A/cm^2$ and emission current reveals the Fowler-Nordheim mode.

• Journal of Information Display
• /
• v.3 no.2
• /
• pp.26-30
• /
• 2002

Large area plasma source has been built for LCD etcher by an array of $2{\times}2$ ICP sources. Since only one RF power supply and one impedance matching network is used in this configuration, any difference in impedances of unit RF antennas causes unbalanced power delivery to the unit ICP. In order to solve this unavoidable unbalance, unit antenna is designed to have a movable tap, with which the inductance of each unit can be adjusted individually. The plasma density becomes symmetric and etch rate becomes more uniform with the impedance adjustment. The concept of adding axial time-varying magnetic field to the single ICP source is applied to the array ICP source, and is found to be effective in terms of etch rate and uniformity.

• Journal of the Semiconductor & Display Technology
• /
• v.9 no.2
• /
• pp.15-20
• /
• 2010

This paper deals with minimizing layout area of FPGA design. FPGAs are becoming increasingly important in the design of ASICs since they provide both large scale integration and user-programmability. This paper describes a method to obtain tight bound on the worst-case increase in area when drivers are introduced along many long wires in a layout. The area occupied by minimum-area embedding for a circuit can depend on the aspect ratio of the bounding rectangle of the layout. This paper presents a separator-based area-optimal embeddings for FPGA graphs in rectangles of several aspect ratios which solves the longest path problem in the constraint graph.

• Journal of the Korean Society for Precision Engineering
• /
• v.29 no.6
• /
• pp.640-647
• /
• 2012

Current electronic products are dominated by the laser processing and the application will be extended this time. Especially, demands for high precision laser processing with a large area has been increasing for a number of applications such as in solar cell battery, display parts, electronic component and automobile industry. In this paper we designed an on-the-fly system for ultrafast/high precision/large area laser processing. In addition, we have developed the path algorithm for large area. Expansion of the area in which laser processing is an important factor to handle the ultrafast/wide area processing, it will require a processing path. Processing path is path of 2- axis stage and stage of change in velocity can be smooth as possible. We proposed a path of the user concept using NURBS(Non-Uniform Rational B-Spline)method. Through our experiment with the chopper, was to prove the continuity of edge parts. Through basic shape experiments, we proved that large area can be processed using laser. We developed a simulation tool using Visual C++.

• Journal of the Semiconductor & Display Technology
• /
• v.11 no.1
• /
• pp.7-11
• /
• 2012

One dimensional and two dimensional nano patterns were fabricated on a 4-inch substrate by Laser Interference Lithography (LIL). Mach-Zehnder interferometer was setup to obtain the interference patterns and adjusted the pattern sizes with change of incident angle. We could obtain a periodic structure with a period of 440 nm using 266 nm laser, and demonstrated a pattern size with $293{\pm}25nm$ over a 4-inch substrate.

• ETRI Journal
• /
• v.34 no.4
• /
• pp.542-552
• /
• 2012

In this paper, a gaze estimation method is proposed for use with a large-sized display at a distance. Our research has the following four novelties: this is the first study on gaze-tracking for large-sized displays and large Z (viewing) distances; our gaze-tracking accuracy is not affected by head movements since the proposed method tracks the head by using a near infrared camera and an infrared light-emitting diode; the threshold for local binarization of the pupil area is adaptively determined by using a p-tile method based on circular edge detection irrespective of the eyelid or eyelash shadows; and accurate gaze position is calculated by using two support vector regressions without complicated calibrations for the camera, display, and user's eyes, in which the gaze positions and head movements are used as feature values. The root mean square error of gaze detection is calculated as $0.79^{\circ}$ for a 30-inch screen.

• Journal of Korea Multimedia Society
• /
• v.19 no.8
• /
• pp.1479-1486
• /
• 2016

According to the advancement of display devices, the multi-screen contents display environment is growing to be accepted for the display exhibition area. The objectives of this research are to find communications technology and to design an editor interface of contents delivery system for the larger and adaptive multi-display workspaces. The proposed system can find existence of display devices and get information without any additional tools like marker, and can recognize device layout with only web-cam and image processing technology. The multi-display contents delivery system is composed of devices with three roles; display device, editor device, and fixed server. The editor device which has the role of main control uses UPnP technology to find existence and receive information of display devices. extract appointed color in captured picture using a tracking library to recognize the physical layout of display devices. After the device information and physical layout of display devices are connected, the content delivery system allows the display contents to be sent to the corresponding display devices through WebSocket technology. Also the experimental results show the possibility of our device connection and layout recognition techniques can be utilized for the large spaced and adaptive multi-display applications.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2007.08a
• /
• pp.85-86
• /
• 2007

As the manufacturing capacity needs for large size LCD TV shifts very fast into next generation, equipment manufactures face more challenges in development of the systems which can accommodate productivity, reliability and high process quality requirements from the panel makers. AKT committed to continue its contribution to the growth of the LCD market by providing excellent PECVD products. The cost containment and performance improvement are key challenges for large size processing equipment development and this presentation discusses various challenges and AKT's solutions in developing large size PECVD equipment beyond Gen. 8.

• The Transactions of the Korea Information Processing Society
• /
• v.6 no.5
• /
• pp.1351-1361
• /
• 1999

The wide spread of multimedia system demands a large area viewing display device which can inform a message to many people in open area. This paper is about the design of a large area viewing LED panel control system. The control system runs on 16 bit microprocessor MC68EC000 and has following functions: 16 line clock and time, 2 channel priority interrupt, 2 channel direct memory access, 2 channel 12 bit clock and timer, 2 channel infrared remocon receiver, 2 channel RS-232C with 16 byte FIFO, IBM PC/AT compatible keyboard interface, ISA bus, battery backuped real time clock, battery backuped 256 byte SRAM and watch dog timer. The core circuits are implemented to ASIC, considering lower cost, higher reliability, higher performance, smaller dimension, and lower power consumption. This is verified by simulation and fabricated in 0.6 um CMOS SOG processes. The total gate count is 39,083 and the clock frequency is 48 MGz. The fabricated ASIC is mounted on test board.