• International Journal of Air-Conditioning and Refrigeration
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• v.15 no.3
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• pp.114-121
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• 2007

In this study, a modified reverse flow type, one of the triple effect absorption cycles, is studied for performance improvement. The cycle simulation is carried out by using EES(Engineering Equation Solver) program for the working fluid of $H_2O/LiBr$ solution. The split-ratios of solution flow rate, UA of each component, pumping mass flow rate of solution are considered as key parameters. The results show that the optimal SRH (split ratio of high side) and SRL (split ratio of low side) values are 0.596 and 0.521, respectively. Under these conditions, the COP is maximized to 2.1. The optimal pumping mass flow rate is selected as 3 kg/s and the corresponding UAEV A is 121 kW/K in the present system. The present simulation results are compared to the other literature results from Kaita's (2002) and Cho's (1998) triple effect absorption systems. The present system has a lower solution temperature and a higher COP than the Kaita's modified reverse flow, and it also gives a higher COP than the Cho's parallel flow by adjusting split ratios.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1296-1299
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• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.

• Nuclear Engineering and Technology
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• v.56 no.3
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• pp.1002-1012
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• 2024

To remove insoluble fission products, which could possibly cause reactor instability and significantly reduce heat transfer efficiency from primary system of molten salt reactor, a helium bubbling method is employed into a passive molten salt fast reactor. In this regard, two-phase flow behavior of molten salt and helium bubbles was investigated experimentally because the helium bubbles highly affect the circulation performance of working fluid owing to an additional drag force. As the helium flow rate is controlled, the change of key thermal-hydraulic parameters was analyzed through a two-phase experiment. Simultaneously, to assess the applicability of numerical model for the analysis of two-phase flow behavior, the numerical calculation was performed using the OpenFOAM 9.0 code. The accuracy of the numerical analysis code was evaluated by comparing it with the experimental data. Generally, numerical results showed a good agreement with the experiment. However, at the high helium injection rates, the prediction capability for void fraction of helium bubbles was relatively low. This study suggests that the multiphaseEulerFoam solver in OpenFOAM code is effective for predicting the helium bubbling but there exists a room for further improvement by incorporating the appropriate drag flux model and the population balance equation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.48-55
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• 2009

This paper presents a high-speed Forward Error Correction (FEC) architecture based on three-parallel Reed-Solomon (RS) decoder for next-generation 100-Gb/s optical communication systems. A high-speed three-parallel RS(255,239) decoder has been designed and the derived structure can also be applied to implement the 100-Gb/s RS-FEC architecture. The proposed 100-Gb/s RS-FEC has been implemented with 0.13-${\mu}m$ CMOS standard cell technology in a supply voltage of 1.2V. The implementation results show that 16-Ch. RS-FEC architecture can operate at a clock frequency of 300MHz and has a throughput of 115-Gb/s for 0.13-${\mu}m$ CMOS technology. As a result, the proposed three-parallel RS-FEC architecture has a much higher data processing rate and low hardware complexity compared with the conventional two-parallel, three-parallel and serial RS-FEC architectures.