• Journal of information and communication convergence engineering
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• v.5 no.1
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• pp.42-44
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• 2007

The a-Si:H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si:H TFTs is inverted staggered. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr) $1500{\AA}$ under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these, thin films is formed with a-SiN:H ($2000{\mu}m$), a-Si:H($2000{\mu}m$) and $n^+a-Si:H$ ($500{\mu}m$). We have deposited $n^+a-Si:H$, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the $n^+a-Si:H$ layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFTs decreasing parasitic capacitance of source-drain show drain current of $8{\mu}A$ at 20 gate voltages, $I_{on}/I_{off}$ ratio of ${\sim}10^8$ and $V_{th}$ of 4 volts.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.821-825
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• 2004

The a-Si：H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si：H TFTs is inverted staggered. The gate electrode is formed by patterning with length of 8 ${\mu}m∼16 ${\mu}m. and width of 80∼200 ${\mu}m after depositing with gate electrode (Cr) 1500 under coming 7059 glass substrate. We have fabricated a-SiN：H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN：H (2000 ), a-Si：H(2000 ) and n+a-Si：H (500). We have deposited n+a-Si：H ,NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si：H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si：H TFTs decreasing parasitic capacitance of source-drain has channel length of 8 ~20 ${\mu}m and channel width of 80∼200 ${\mu}m. And it shows drain current of 8 ${\mu}A at 20 gate voltages, Ion/Ioff ratio of 108 and Vth of 4 volts.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1393-1398
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• 2009

Conventionally, etching is first considered for microelectronics fabrication process and is specially important in process of a-Si:H thin film transistor for LCD. In this paper, we stabilize properties of device by development of wet and dry etching process. The a-Si:H TFTs of this paper is inverted staggered type. The gate electrode is lower part. The gate electrode is formed by patterning with length of 8 ${\mu}$m${\sim}$16 ${\mu}$m and width of 80${\sim}$200 ${\mu}$m after depositing with gate electrode (Cr) 1500 ${\AA}$under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photo resistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN:H (2000 ${\mu}$m), a-Si:H(2000 ${\mu}$m) and n+a-Si:H (500 ${\mu}$m), We have deposited n-a-Si:H, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. In the fabricated TFT, the most frequent problems are over and under etching in etching process. We were able to improve properties of device by strict criterion on wet, dry etching and cleaning process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.6
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• pp.1099-1103
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• 2007

TFT's have been intensively researched for possible electronic and display applications. Through tremendous engineering and scientific efforts, a-Si:H TFT fabrication process was greatly improved. In this paper, the reason on defects occurring at a-Si:H TFT fabrication process is analyzed and solved, so a-Si:H TFT's yield is increased and reliability is improved. The a-Si:H TFT of this paper is inverted staggered type TFT. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr). We have fabricated a-SiN:H, conductor, etch-stopper and photo-resistor on gate electrode in sequence, respectively. We have deposited n+a-Si:H, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-slower pattern. The NPR layer by inverting pattern of upper Sate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFT made like this has problems at photo-lithography process caused by remains of PR. When sample is cleaned, this remains of PR makes thin chemical film on surface and damages device. Therefor, in order to improve this problem we added ashing process and cleaning process was enforced strictly. We can estimate that this method stabilizes fabrication process and makes to increase a-Si:H TFT's yield.