• Title/Summary/Keyword: interleaving

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Design of Efficient frequency Offset Estimator for MB-OFDM based UWB Systems (MB-OFDM 기반 UWB 시스템을 위한 효율적인 주파수 옵셋 추정기의 설계)

  • Kim, Kil-Hwan;Jung, Yun-Ho;Kim, Jae-Seok
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.3C
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    • pp.311-321
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    • 2009
  • This paper proposes an efficient frequency offset estimation algorithm for MB-OFDM based UWB systems. The time-frequency interleaving in MB-OFDM extends the time-interval between two transmitted OFDM symbols in the same sub-band. The extended time-interval causes not only the degradation of the system performance by reducing frequency offset estimation range, but also the increase of the hardware complexity by requiring the larger number of storing samples. The proposed estimation algorithm expands the estimation range by applying the proposed sign detection scheme. Simulation results show that the estimation range is increased above 30 ppm compared with a conventional auto-correlation based scheme. The estimation is performed on only one sub-band, and the frequency offsets of the others are calculated by relation to center frequency. This way reduced the number of the storing samples by about l/3. The frequency offset estimator with the proposed algorithm was designed into the architecture which minimizes hardware overhead by time-sharing operators and memory units, and which was synthesized to gate-level circuits using $0.13{\mu}m$ CMOS technology, and the total gates were about 47K.

Performance Analysis of RS, Turbo and LDPC Code in the Binary Symmetric Erasure Channel (이진 대칭 소실 채널에서 RS, 터보 및 저밀도 패리티 검사 부호의 성능 분석)

  • Lim, Hyung-Taek;Park, Myung-Jong;Kang, Seog-Geun;Joo, Eon-Kyeong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.2C
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    • pp.219-228
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    • 2010
  • In this paper, performance of RS (Reed-Solomon), turbo and LDPC (low density parity check) code in the binary symmetric erasure channel is investigated. When the average erasure length is reduced, the frequency of short erasures is increased. The RS code shows serious performance degradation in such an environment since decoding is carried out symbol-by-symbol. As the erasure length is increased, however, the RS code shows much improved en-or performance. On the other hand, the message and corresponding parity symbols of the turbo code can be erased at the same time for the long erasures. Accordingly, iterative decoding of the turbo code can not improve error performance any more for such a long erasure. The LDPC code shows little difference in error performance with respect to the variation of the average erasure length due to the virtual interleaving effect. As a result, the LDPC code has much better erasure decoding performance than the RS and turbo code.

Motion Vector Recovery Scheme for H.264/AVC (H.264/AVC을 위한 움직임 벡터 복원 방법)

  • Son, Nam-Rye
    • The Journal of the Korea Contents Association
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    • v.8 no.5
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    • pp.29-37
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    • 2008
  • To transmit video bit stream over low bandwidth such as wireless channel, high compression algorithm like H.264 codec is exploited. In transmitting high compressed video bit-stream over low bandwidth, packet loss causes severe degradation in image quality. In this paper, a new algorithm for recovery of missing or erroneous motion vector is proposed. Considering that the missing or erroneous motion vectors in blocks are closely correlated with those of neighboring blocks. Motion vector of neighboring blocks are clustered according to average linkage algorithm clustering and a representative value for each cluster is determined to obtain the candidate motion vector sets. As a result, simulation results show that the proposed method dramatically improves processing time compared to existing H.264/AVC. Also the proposed method is similar to existing H.264/AVC in terms of visual quality.

Evaluation and Analysis of Scheduling Algorithms for Peak Power Reduction (전력 피크 감소를 위한 스케줄링 알고리즘의 성능 평가 및 분석)

  • Sung, Minyoung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.16 no.4
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    • pp.2777-2783
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    • 2015
  • Peak power reduction is becoming increasingly important not only for grid operators but also for residential users. The scheduling of electric loads tries to reduce the power peak by splitting the power-on period of an electric device into multiple smaller ones and by interleaving the on-periods of every device in a holistic way. This paper analyzes the performance of EDF, LSF, TCBM, and lazy scheduling algorithms and proposes the enhancement schemes. For analysis, we have implemented the scheduling policies in a simulation environment for distributed control systems. Through extensive experiments using real power traces, we discuss their performance characteristics in terms of power deviation, switch count, and temperature violation ratio. To prevent excessive switching, we propose to employ the concept of limited preemptibility and evaluate its effect on performance. It is found that the best performance is achieved when the scheduler capacity is dynamically adjusted to the actual power demand. The experiment results show that, by load scheduling, the probability of having a power deviation greater than 150W is reduced from 21.5% down to 3.2%.

Design and Implementation of Modulator Channel Card and VLSI Chip for a Wideband CDMA Wireless Local Loop System (광대역 CDMA WLL 시스템을 위한 변조기 채널 카드 및 VLSI 칩 설계 및 구현)

  • 이재호;강석봉;조경록
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.10A
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    • pp.1571-1578
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    • 1999
  • In this paper, we present the Modulator Channel Card and VLSI chip for the Radio Transceiver Unit (RTU) of direct sequence code division multiple access (DS-CDMA) Wireless Local Loop (WLL) System. The Modulator Channel Card is designed and implemented using ASIC's, FPGA's and DSP's. The ASIC, compliance with Common Air Interface specification proposed by ETRI, has 40K gates which is designed to operate at 32MHz, and is fabricated using $0.6\mu\textrm{m}$ CMOS process. The ASIC carries out for I- or Q- phase data channel signal processing at a time, where each data channel processing consists of channel coding, block interleaving, scrambling, Walsh modulation, Pseudo-Noise (PN) spreading, and baseband filtering. The Modulator Channel Card has been integrated as a part of RTU of WLL system and is confirmed that it meets all functional and performance requirements.

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Optimum Interleaver Design and Performance Analysis of Double-Binary Turbo Code for Wireless Metropolitan Area Networks (WMAN 시스템의 이중 이진 구조 터보부호 인터리버 최적화 설계 및 성능 분석)

  • Park, Sung-Joon
    • Journal of the Korea Society for Simulation
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    • v.17 no.1
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    • pp.17-22
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    • 2008
  • Double-binary turbo code has been adopted as an error control code of various future communication systems including wireless metropolitan area networks(WMAN) due to its powerful error correction capability. One of the components affecting the performance of turbo code is internal interleaver. In 802.16 d/e system, an almost regular permutation(ARP) interleaver has been included as a part of specification, however it seems that the interleaver is not optimized in terms of decoding performance. In this paper, we propose three optimization methods for the interleaver based on spatial distance, spread and minimum distance between original and interleaved sequence. We find optimized interleaving parameters for each optimization method and evaluate the performances of the proposed methods by computer simulation under additive white Gaussian noise(AWGN) channel. Optimized parameters can provide up to 1.0 dB power gain over the conventional method and furthermore the obtainable gain does not require any additional hardware complexity.

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Efficient Architecture of an n-bit Radix-4 Modular Multiplier in Systolic Array Structure (시스톨릭 어레이 구조를 갖는 효율적인 n-비트 Radix-4 모듈러 곱셈기 구조)

  • Park, Tae-geun;Cho, Kwang-won
    • The KIPS Transactions:PartA
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    • v.10A no.4
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    • pp.279-284
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    • 2003
  • In this paper, we propose an efficient architecture for radix-4 modular multiplication in systolic array structure based on the Montgomery's algorithm. We propose a radix-4 modular multiplication algorithm to reduce the number of iterations, so that it takes (3/2)n+2 clock cycles to complete an n-bit modular multiplication. Since we can interleave two consecutive modular multiplications for 100% hardware utilization and can start the next multiplication at the earliest possible moment, it takes about only n/2 clock cycles to complete one modular multiplication in the average. The proposed architecture is quite regular and scalable due to the systolic array structure so that it fits in a VLSI implementation. Compared to conventional approaches, the proposed architecture shows shorter period to complete a modular multiplication while requiring relatively less hardware resources.

Interleaving Phenomena of the North Pacific Intermediate Water in the Offshore Area of the Kuroshio

  • Yang, Sung-Kee;Lee, Byung-Gul
    • Journal of Environmental Science International
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    • v.12 no.5
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    • pp.521-527
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    • 2003
  • To study the intruded phenomena of North Pacific Ocean around Boso peninsular, water property distribution in the adjacent seas to Japan is studied using the hydrographic data obtained by Japan Maritime Agency and Japan Fisheries Agency from 1973 to 1996, The scattering of water type in T-5 diagram is relatively small in the Kuroshio Region. Both the envelopes of saline side and of fresh side of the scattered data points shifts gradually from saline side to fresh side as the observation Line moves from southwest to northeast. In mixed water region, the scattering of water type increases rapidly as the observation line moves north; the envelope of fresh cold side moves towards fresh cold side much faster than that of saline side. This suggests that the water does not advect along the salinity minimum layer, but the salinity minimum layer can be understood as a boundary of two different waters aligned vertically, We defined the typical water masses as the Oyashio Water and the Kuroshio Water. The water mass below the salinity minimum layer may be created by isopycnal mixing of these two water masses with a fixed mixing rate. While the water mass above the salinity minimum cannot be created simply by isopycnal mixing. The salinity minimum layer may be eroded from upper side due to active minxing processes in the surface layer, while the water of the salinity minimum layer moves gradually southward. This appears to give an explanation why the thermosteric anomaly value at salinity minimun decereases towards south.

Comparisions of stream activation mechanisms in computer based teleconferencing systems for low delay (지연 축소를 위한 컴퓨터 영상회의 시스템의 시트림 동작 구조 비교)

  • Lee, Gyeong-Hui;Kim, Du-Hyeon;Gang, Min-Gyu;Jeong, Chan-Geun
    • The Transactions of the Korea Information Processing Society
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    • v.4 no.2
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    • pp.363-376
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    • 1997
  • In this paper, we present a hardware architecture and a sofrware architecture for cimputer based teleconferencing systems.And also we analyse stream adtivation mechanisms for them form the viewpoint of delay. MuX that is a multimedia I/O server provides various processing elements for data I/O, synchronization, interleaving and mixing.We describe methods to build teleconferencing systems with the elements and compares the technique using master click with the techniquie using self clock.In the plase of dta input.the technique using self click is berrer than the technique using master clock.When we generate interleved stream from audio and video stream and activate channel objects by periodic audio stream as activation clock, dealy from imput audio stream to imterleved stream is reduced but delay for video stream is not reduced as much as in the case of audio stream.

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Block Turbo Codes for High Order Modulation and Transmission Over a Fast Fading Environment (고차원변조 방식 및 고속 페이딩 전송 환경을 위한 블럭터보부호)

  • Jin, Xianggunag;Kim, Soo-Young;Kim, Won-Yong;Cho, Yong-Hoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.37 no.6A
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    • pp.420-425
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    • 2012
  • A forward error correction (FEC) coding techniques is one of time diversity techniques with which the effect of channel impairments due to noise and fading are spreaded over independently, and thus the performance could be improved. Therefore, the performance of the FEC scheme can be maximized if we minimize the correlation of channel information across over a codeword. In this paper, we propose a block turbo code with the maximized time diversity effect which may be reduced due to utilization of high order modulation schemes and due to transmission over a comparatively fast fading environment. Especially, we propose a very simple formula to calculate the address of coded bit allocation, and thus we do not need any additional outer interleavers, i.e., inter-codeword interleavers. The simulation resuts investigated in this paper reveal that the proposed scheme can provide the performance gain of more than a few decibels compared to the conventional schemes.