• Title/Summary/Keyword: interface state density

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Insertion of an Organic Hole Injection Layer for Inverted Organic Light-Emitting Devices

  • Park, Sun-Mi;Kim, Yun-Hak;Lee, Yeon-Jin;Kim, Jeong-Won
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.02a
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    • pp.379-379
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    • 2010
  • Recent technical advances in OLEDs (organic light emitting devices) requires more and more the improvement in low operation voltage, long lifetime, and high luminance efficiency. Inverted top emission OLEDs (ITOLED) appeared to overcome these problems. This evolved to operate better luminance efficiency from conventional OLEDs. First, it has large open area so to be brighter than conventional OLEDs. Also easy integration is possible with Si-based driving circuits for active matrix OLED. But, a proper buffer layer for carrier injection is needed in order to get a good performance. The buffer layer protects underlying organic materials against destructive particles during the electrode deposition and improves their charge transport efficiency by reducing the charge injection barrier. Hexaazatriphenylene-hexacarbonitrile (HAT-CN), a discoid organic molecule, has been used successfully in tandem OLEDs due to its high workfunction more than 6.1 eV. And it has the lowest unoccupied molecular orbital (LUMO) level near to Fermi level. So it plays like a strong electron acceptor. In this experiment, we measured energy level alignment and hole current density on inverted OLED structures for hole injection. The normal film structure of Al/NPB/ITO showed bad characteristics while the HAT-CN insertion between Al and NPB greatly improved hole current density. The behavior can be explained by charge generation at the HAT-CN/NPB interface and gap state formation at Al/HAT-CN interface, respectively. This result indicates that a proper organic buffer layer can be successfully utilized to enhance hole injection efficiency even with low work function Al anode.

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Nonlinear Analysis of Shear Behavior on Pile-Sand Interface Using Ring Shear Tests (링전단시험을 이용한 말뚝 기초-사질지반 간 인터페이스 거동 분석)

  • Jeong, Sang-Seom;Jung, Hyung-Suh;Whittle, Andrew;Kim, Do-Hyun
    • Journal of the Korean Geotechnical Society
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    • v.37 no.5
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    • pp.5-17
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    • 2021
  • In this study, the shear behavior between pile-sandy soil interface was quantified based on series of rigorous ring shear test results. Ring shearing test was carried out to observe the shear behavior prior to failure and behavior at residual state between most commonly used pile materials - steel and concrete - and Jumunjin sand. The test was set to clarify the shear behavior under various confinement conditions and soil densities. The test results were converted in to representative friction angles for various test materials. Additional numerical analysis was executed to validate the accuracy of the test results. Based on the test results and the numerical validation, it was found that due to the dilative and contractive nature of sand, its interface behavior can be categorized in to two different types : soils with higher densities tend to show peak shear stress and moves on to residual state, while on the other hand, soils with lower densities tend to show bilinear load-transfer curves along the interface. However, the relative density and the confining stress was found to affect the friction angle only in the small train range, and converges as it progresses to large deformation. This study established a large deformation analysis method which can successfully simulate and predict the large deformation behavior such as ring shear tests. Moreover, the friction angle derived from the ring shear test result and verified by numerical analysis can be applied to numerical analysis and actual design of various pile foundations.

The Characteristics Analysis of GIDL current due to the NBTI stress in High Speed p-MOSFET (고속용 p-MOSFET에서 NBTI 스트레스에 의한 GIDL 전류의 특성 분석)

  • Song, Jae-Ryul;Lee, Jong-Hyung;Han, Dae-Hyun;Lee, Yong-Jae
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.13 no.2
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    • pp.348-354
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    • 2009
  • It has analyzed that the device degradation by NBTI (Negative Bias Temperature Instability) stress induced the increase of gate-induced-drain-leakage(GIDL) current for p-MOSFETs. It is shown that the degradation magnitude, as well as its time, temperature, and field dependence, is govern by interface traps density at the silicon/oxide interface. from the relation between the variation of threshold voltage and subthreshold slope, it has been found that the dominant mechanism for device degradation is the interface state generation. From the GIDL measurement results, we confined that the EHP generation in interface state due to NBTI stress led to the increase of GIDL current. Therefore, one should take care of the increased GIDL current after NBTI stress in the ultra-thin gate oxide device. Also, the simultaneous consideration of reliability characteristics and dc device performance is highly necessary in the stress engineering of nanoscale CMOSFETs.

Electrical Characteristics on MOS Structure with Irradiation of Radiation (방사선이 조사된 MOS구조에서의 전기적 특성)

  • 임규성;고석웅;정학기
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2001.10a
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    • pp.644-647
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    • 2001
  • The investigations were discussed on the radiation effects of the electrical properties to the p-type MOS capacitors, which were irradiated by cobalt-60 gamma ray sources. The characteristics of capacitance-bias voltage(C-V) and of dielectric dissipation tarter-bias voltage(D-V) on the capacitors were measured at 1 [MHz] frequency. The microscopic behaviors of spate charges in oxide and silicon-silicon dioxide(Si- $SiO_2$) interface were investigated from the experimental data. The C-V characteristics are statical and convenient for the evaluation of the steady state behavior of carriers and interface states characteristics. While, the distribution and magnitude of space charges in oxide can be found out accurately on the $V_{dp}$ in D-V curves. The density of interface states can be deduced with ease from the magnitude of D-peak at depletion state. Thus, it is also concluded that the D-V curves are more useful and easier than conventional C-V curves for analysis of the microscopic and dynamic behavior of carriers in oxide and Si- $SiO_2$interface.

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Feasibility Study on the Gas-Liquid Multiphase by Lattice-Boltzmann Method in Two-Dimensions (Lattice-Boltzmann Method를 이용한 2차원 기체-액체간 거동 기초 연구)

  • Jung, Rho-Taek
    • Journal of the Korean Society for Marine Environment & Energy
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    • v.19 no.2
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    • pp.111-119
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    • 2016
  • Gas-Liquid multiphase flow simulation has been carried out using the Lattice boltzmann method. For the interface treatment, pseudo-potential model (Shan-Chen) was used with the Carnahan-Starling equation of state. Exact Difference Method also applied for the treatment of the force term. Through the developed code, we simulated coexsitence structure of high and low density, phase separation, surface tension effect, characteristics of moving interface, homogeneous and heterogeneous cavitation and bubble collaps.

Improvement of Electrical Properties of Diamond MIS (Metal-Insulator- Semiconductor) Interface by Gate Insulator and Application to Metal-Insulator- Semiconductor Field Effect Transistors (게이트 절연막에 의한 다이아몬드 MIS (Metal-Insulator-Semiconductor) 계면의 전기적 특성 개선과 전계효과 트랜지스터에의 응용)

  • Yun, Young
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.14 no.6
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    • pp.648-654
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    • 2003
  • Diamond MIS(Metal-Insulator-Semiconductor) diodes and MISFETs(Metal-Insulator-Semiconductor Field Effect Transistors) were fabricated by employing various fluorides as gate insulator, and their electrical properties were closely investigated by means of C-V measurements. The A1/BaF$_2$/diamond MIS structure exhibited outstanding electrical properties. The MIS diode showed a very low surface state density of ∼10$\^$10//$\textrm{cm}^2$ eV near the valence band edge, and the observed effective mobility(${\mu}$$\_$eff/) of the MISFET was 400 $\textrm{cm}^2$/Vs, which is the highest value obtained until now in the diamond FET. From the chemiphysical point of view, the above result might be explained by the reduction of adsorbed-oxygen on the diamond surface via strong chemical reaction by the constituent Ba atom in the insulator during the film deposition(Oxygen-Gettering Effect).

A study on the characteristics of double insulating layer (HgCdTe MIS의 이중 절연막 특성에 관한 연구)

  • 정진원
    • Electrical & Electronic Materials
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    • v.9 no.5
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    • pp.463-469
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    • 1996
  • The double insulating layer consisting of anodic oxide and ZnS was formed for HgCdTe metal insulator semiconductor(MIS) structure. ZnS was evaporated on the anodic oxide grown in H$_{2}$O$_{2}$ electrolyte. Recently, this insulating mechanism for HgCdTe MIS has been deeply studied for improving HgCdTe surface passivation. It was found through TEM observation that an interface layer is formed between ZnS and anodic oxide layers for the first time in the study of this area. EDS analysis of chemical compositions using by electron beam of 20.angs. in diameter and XPS depth composition profile indicated strongly that the new interface is composed of ZnO. Also TEM high resolution image showed that the structure of oxide layer has been changed from the amorphous state to the microsrystalline structure of 100.angs. in diameter after the evaporation of ZnS. The double insulating layer with the resistivity of 10$^{10}$ .ohm.cm was estimated to be proper insulating layer of HgCdTe MIS device. The optical reflectance of about 7% in the region of 5.mu.m showed anti-reflection effect of the insulating layer. The measured C-V curve showed the large shoft of flat band voltage due to the high density of fixed oxide charges about 1.2*10$^{12}$ /cm$^{2}$. The oxygen vacancies and possible cationic state of Zn in the anodic oxide layer are estimated to cause this high density of fixed oxide charges.

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Trap characteristics of charge trap type NVSM with reoxidized nitrided oxide gate dielectrics (재산화 질화산화 게이트 유전막을 갖는 전하트랩형 비휘발성 기억소자의 트랩특성)

  • 홍순혁;서광열
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.12 no.6
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    • pp.304-310
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    • 2002
  • Novel charge trap type memory devices with reoxidized oxynitride gate dielectrics made by NO annealing and reoxidation process of initial oxide on substrate have been fabricated using 0.35 $\mu \textrm{m}$ retrograde twin well CMOS process. The feasibility for application as NVSM memory device and characteristics of traps have been investigated. For the fabrication of gate dielectric, initial oxide layer was grown by wet oxidation at $800^{\circ}C$ and it was reoxidized by wet oxidation at $800^{\circ}C$ after NO annealing to form the nitride layer for charge trap region for 30 minutes at $850^{\circ}C$. The programming conditions are possible in 11 V, 500 $\mu \textrm{s}$ for program and -13 V, 1ms for erase operation. The maximum memory window is 2.28 V. The retention is over 20 years in program state and about 28 hours in erase state, and the endurance is over $3 \times 10^3$P/E cycles. The lateral distributions of interface trap density and memory trap density have been determined by the single junction charge pumping technique. The maximum interface trap density and memory trap density are $4.5 \times 10^{10} \textrm{cm}^2$ and $3.7\times 10^{18}/\textrm{cm}^3$ respectively. After $10^3$ P/E cycles, interlace trap density increases to $2.3\times 10^{12} \textrm{cm}^2$ but memory charges decreases.

Parametric Study for Excimer Laser-induced Crystallization in the a-Si thin film

  • Moon, Min-Hyung;Kim, Hyun-Jae;Choi, Kwang-Soo;Souk, Jun-Hyung;Seo, Chang-Ki;Kim, Do-Young;Dhungel, Suresh Kumar;Yi, Junsin
    • 한국정보디스플레이학회:학술대회논문집
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    • 2003.07a
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    • pp.630-633
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    • 2003
  • Integrating the driver circuitry directly onto the glass substrate would be one of the advantages of polycrystalline Si (poly-Si) TFT-(LCD). Low-temperature poly-Si TFT(LTPS) is well-suited for higher-definition display applications due to its intrinsically superior electrical characteristics. In order to improve LTPS electrical characteristics, currently the excimer laser-induced crystallization (ELC) processes and sequential lateral solidification method were developed. Grain size of the poly-Si is mainly affected by beam pitch and energy density. Key parameter for making a larger poly-Si using excimer laser annealing(ELA) and increasing a throughput is due to increase in beam pitch and energy density to a certain degree. Furthermore, thin $SiO_{2}$ capping is effective to suppress the protrusion of the poly-Si thin films and to reduce the interface state density. From the ELA process, we are able to control grain size by varying different parameters such as number of shots and energy density.

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The characteristics of MIS BST thin film capacitor

  • Park, Chi-Sun;Kim, In-Ki
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.11 no.1
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    • pp.38-42
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    • 2001
  • Electric and dielectric(Ba,Sr)$TiO_3$[BST] thin films for emtal-Insulator-Semiconductor(MIS) capacitors have been studied. BST thin films wre deposted on p-Si(100) substrates bythe RF magnetron sputtering with tempratue range of 500~$600^{\circ}C$. The dielectric properties of MIS capacitors consisting of Al/BST/$SiO_2$/Si sandwich structure were evaluated ot redcue the leakage current density. The charge state densities of the MIS capacitors were determined by high frequency (1 MHz) C-V measurement. In order to reduce the leakage current in MIS capacitor, high quality $SiO_2$ layer was deposited on bare p-Si substrate. Depending on the oxygen pressure and substrate temperature both positive and negative polarities of effective oxide charge in the MIS capacitors were evaluated. It is considered that the density of electronic states, generated at the BST/$SiO_2$/p-Si interface due to the asymmetric structure within BST/$SiO_2$/Si structure, and the oxygen vacancy content has influence on the behavior of oxide charge.

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