• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.180-180
• /
• 2010

Thin film transistors (TFTs) based on oxide semiconductors have emerged as a promising technology, particularly for active-matrix TFT-based backplanes. Currently, an amorphous oxide semiconductor, such as InGaZnO, has been adopted as the channel layer due to its higher electron mobility. However, accurate and repeatable control of this complex material in mass production is not easy. Therefore, simpler polycrystalline materials, such as ZnO and $SnO_2$, remain possible candidates as the channel layer. Inparticular, ZnO-based TFTs have attracted considerable attention, because of their superior properties that include wide bandgap (3.37eV), transparency, and high field effect mobility when compared with conventional amorphous silicon and polycrystalline silicon TFTs. There are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems, the stability of ZnO-based TFTs, is as yet unsolved since ZnO-based TFTs usually contain defects in the ZnO channel layer and deep level defects in the channel/dielectric interface that cause problems in device operation. The quality of the interface between the channel and dielectric plays a crucial role in transistor performance, and several insulators have been reported that reduce the number of defects in the channel and the interfacial charge trap defects. Additionally, ZnO TFTs using a high quality interface fabricated by a two step atomic layer deposition (ALD) process showed improvement in device performance In this study, we report the fabrication of high performance ZnO TFTs with a $Si_3N_4$ gate insulator treated using plasma. The interface treatment using electron cyclotron resonance (ECR) $O_2$ plasma improves the interface quality by lowering the interface trap density. This process can be easily adapted for industrial applications because the device structure and fabrication process in this paper are compatible with those of a-Si TFTs.

• Transactions on Electrical and Electronic Materials
• /
• v.13 no.4
• /
• pp.188-191
• /
• 2012

This paper introduces a new method regarding deuterium incorporation in the gate dielectric including deuterium implantation and post-annealing at the back-end-of-the process line. The control device and the deuterium furnace-annealed device were also prepared for comparison with the implanted device. It was observed that deuterium implantation at a light dose of $1{\times}10^{12}-1{\times}10^{14}/cm^2$ at 30 keV reduced hot-carrier injection (HCI) degradation and negative bias temperature instability (NBTI) within our device structure due to the reduction in oxide charge and interface trap. Deuterium implantation provides a possible solution to enhance the bulk and interface reliabilities of the gate oxide under the electrical stress.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.11a
• /
• pp.53-53
• /
• 2009

Charge trap flash memory devices with modified tunneling barriers were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were used as engineered tunneling barriers. The VARIOT type tunneling barrier composed of oxide-nitride-oxide (ONO) layers revealed reliable electrical characteristics; long retention time and superior endurance. On the other hand, the CRESTED tunneling barrier composed of nitride-oxide-nitride (NON) layers showed degraded retention and endurance characteristics. It is found that the degradation of NON barrier is associated with the increase of interface state density at tunneling barrier/silicon channel by programming and erasing (P/E) stress.

• Journal of the Ergonomics Society of Korea
• /
• v.15 no.2
• /
• pp.99-111
• /
• 1996

In today's highly automated aircraft, the role of the pilot has changed from an airplane controller to a system manager. As a system manager in a cockpit, today's pilot is in charge of a management-level activity called cockpit task management( CTM). According to earlier studies, pilot errors in performing CTM activities were significant factors in a large number of aircraft accidents and incidents. The primary objective of this research was to reduce CTM-related pilot errors. A prototype pilot- vehicle interface called the cockpit task management system (CTMS) was developed and its effectiveness in improving CTM performance was evaluated. After the CTMS was implemented, it was integrated into a PC-based flight simulator to perform an experiment to evaluate its effectiveness. Eight volunteer subjects were used to collect performance data. The results of the experiment indicated that a statistically significant improvement was observed when the subjects flew with the assistance of the CTMS.

• Journal of the Korean Applied Science and Technology
• /
• v.25 no.4
• /
• pp.518-524
• /
• 2008

In this study, positive plates of lead acid battery of Pb-Ca alloy and Pb-Ca-Sn alloy were fabricated and the mechanical characteristics of positive plates were measured. This study observed how the changes of content of Ca & Sn affect interface corrosion which is located in between grid & active materials and lead acid batteries as well. The mechanical characteristics of grid alloy is better when Ca is 0.05 wt.% then 0.1 wt.%. This study said that the corrosion rate between the active material based on the charge/discharge cycle of lead acid battery and grid interface is much faster than a grid which contains Sn. And furthermore, according to the study the rate 30 of Sn/Ca which is added to grid shows the best performance.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2017.05a
• /
• pp.169-169
• /
• 2017

Due to key roles for the electrochemical stability and charge capacity the solid-electrolyte interphase (SEI) has been extensively studied in anodes of a Li-ion battery cell. There is, however, few of investigation for cathodes. Using first-principles based calculations we describe atomic-level process of the SEI layer formation at the interface of a carbonate electrolyte and $LiMn_2O_4$ spinel cathode. Furthermore, using beyond the conventional density functional theory (DFT+U) calculations we examine the work function of the cathode and frontier orbitals of the electrolyte. Based on the results we propose that proton transfer at the interface is an essential mechanism initiating the SEI layer formation in the $LiMn_2O_4$. Our results can guide a design concept for stable and high capacity Li-ion battery cell through screening an optimum electrolyte fine-tuned energy band alignment for a given cathode.

• Korean Journal of Food Science and Technology
• /
• v.25 no.5
• /
• pp.521-525
• /
• 1993

To elucidate adsorption of proteins and examine the molecular behavior of protein molecules at interfaces, various proteins at the air-water interface were studied. The adsorption data of bovine serum albumin intermediates indicated that the conformational state of a protein played an important role in adsorption of proteins at interfaces. The adsorption behavior of succinylated beta-lactoglobulin indicated that the increase in the net negative charge of the protein significantly inflenced both the kinetics and thermodynamics of adsorption. The adsorption kinetics of beta-casein showed that the salt that induced break-down of water structure decreased the rate of adsorption.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.6
• /
• pp.107-116
• /
• 1994

In this paper, The electrical properties of MOS capacitors and transistoras with gate of in-situ doped amorphous Si and poly Si doped by POCI$_3$. Under constant current F-N stress, MOS capacitors with in-situ doped amorphous Si gate have shown the best resistance to degradation in reliabilty properties such as increase of leakage current, shift of gate voltage (V$_{g}$). shift of flat band voltage (V$_{fb}$) and charge to breakdown(Q$_{bd}$). Also, MOSFETs with in-situ doped amorphous Si gate have shown to have less degradation in transistor properties such as threshold voltage, transconductance and drain current. These improvements observed in MOS devices with in-situ doped amorphous Si gate is attributed to less local thinning spots at the gate/SiO$_2$ interface, caused by the large grain size and the smoothness of the surface at the gate/SiO$_2$ interface.

• Journal of the Korean Electrochemical Society
• /
• v.5 no.4
• /
• pp.216-220
• /
• 2002

The effects of electrolytes on electrochemical behavior from an oil thin layer interposed between a graphite electrode and an aqueous solution phase were examined. A hydrophobic electroactive species, tetrachloro-1,4-benzoquinone (TCQ), in a benzonitrile (EN) layer was employed to study ion transfer properties across the BN-water interface. Experimental results showed that hydrophobic cations as well as anions could be successfully used as ionic charge carriers. The addition of various salts into either the oil layers or the aqueous solutions offers deeper insight for the electrochemistry of the liquid thin layer system. When aqueous perchloric acid is interfaced with the BN films, the perchlorate ion of tetrahexylammonium perchlorate (THAP) substantially suppresses the dissociated proton concentration in the layer by the common ion effect while there is only a little change in the total acid concentration. Further approach by theoretical calculation makes it possible to quantitatively understand the effect of the electrolytes to the electrochemical responses of TCQ, which were previously reported (Anal. Chem. 73, 337 (2001)).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.3
• /
• pp.181-185
• /
• 2003

Influence of post gate oxidation anneal on Negative Bias Temperature Instability (NBTI) of PMOSFE has been investigated. At oxidation anneal temperature raised above 950$^{\circ}$C, a significant improvement of NBTI was observed which enables to reduce PMO V$\_$th/ shift occurred during a Bias Temperature (BT) stress. The high temperature anneal appears to suppress charge generations inside the gate oxide and near the silicon oxide interface during the BT stress. By measuring band-to-band tunneling currents and subthreshold slopes, reduction of oxide trapped charges and interface states at the high temperature oxidation anneal was confirmed.