• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.612-614
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• 1998

As chip feature size decrease, interconnect delay gains more importance. A accurate timing analysis required to estimate interconnect delay as well as cell delay. In this paper, we present a timing-level delay calculation tool of which the accuracy is bounded within 10% of SPICE results. This delay calculation tool generates delay values in SDF(Standard Delay Format) for parasitic data extracted in SPEF(Standard Parasitic Exchange Format). The efficiency of the tool is easily seen because it uses AWE(Asymptotic Waveform Evaluation) algorithm for interconnect delay calculation, and precharacterized library and effective capacitance model for cell delay calculation.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.1-10
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• 2009

Carbon nanotube(CNT)s have been considered as one of the most unique materials due to the their superior mechanical, thermal and electrical properties. Therefore, numerous studies have been performed for the utilization of CNTs. This review article focuses on the recent research trends on the utilization of CNTs for new interconnect materials in electronics packaging. Major contents mentioned are the direct interconnection technology using CNTs and the main properties of polymer/CNTs composite materials. This article is aimed at the reviewing of important results from the recent studies and providing the straightforward understanding of the results through the mutual analysis and a industrial viewpoint.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.28-32
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• 2004

In this paper, degradation in field-aged PV modules including degradation of interconnect, discoloration of encapsulant and hot spot have been observed and analyzed. From the results, photovoltaic module installed for 6 years shows around 16% drop of electrical properties due to the interconnect degradation and PV module passed 18 years has been found to drop of around 20% mainly by the encapsulant discoloration. Furthermore the difference between low and high temperature of PV array at hot spot goes up to $30^{\circ}C$ and it leads to interconnect degradation. On the other hands, the temperature difference was observed to be around $15^{\circ}C$ at the encapsulant discoloration spot of PV array.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.74-85
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• 2015

PCI Express is a well-known and widely used de-facto system bus standard for connecting among a processor and IO devices. PCI Express is originated from old PCI standard, and its most of applications are limited to be used within a PC or server system. But, because of its fast speed, low power consumption, and good protocol efficiency, it is considered as one of a good candidate for an alternate system interconnect for many years. In this paper, we present design, implementation and early evaluation of an alternate system interconnect by utilizing PCI Express. The developed alternate system interconnect using PCI Express (named PCIeLINK) utilizes non-transparent bridging (NTB) technic which generally used in fail-over system in PCI and PCI Express. By using NTB technic, PCI Express device can be extended to outside of a system without electrical and logical problems arising during system boot and enumeration. To build up an alternate system interconnect, we designed and implemented a network interface card having multiple PCI Express ${\times}4$ connections (theoretically 20 Gbps) and tested, The early test results revealed that an ${\times}4$ port in the card showed 8.6 Gbps peak performance for bulk transmission and 5.1 Gbps peak for normal TCP/IP transfer.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.12a
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• pp.127-154
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• 1999

Interconnect - Wire bonding-> Flip chip interconnect ; At research step, Au stud bump bonding seems to be more proper .Package -Plastic package-> $Z_{0}$ controlled land grid package -Flip Chip will be used for RF ICs and CSP for digital ICs -RF MCM comprised of bare active devices and integrated passive components -Electrical design skills are much more required in RF packaging .Passive Component -discrete-> integrated -Both of size and numbers of passive components must be reduced

• Journal of the Optical Society of Korea
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• v.1 no.1
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• pp.44-47
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• 1997

The integration of a GaAs/AlGaAs multi-quantum well electroabsorption modulator and a tapered waveguide vertical direction optical interconnect has been performed without the complicated regrowth process. Zn impurity-induced layer disordering of MQW layer is used to achieve the energy transfer between SQW and MQW regions. Light coupled into a SQW region was transferred to an MQW region and an intensity modulation of 10 dB extinction ratio was demonstrated.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.160-162
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• 1996

This paper is one-phase fault current analysis of 154kV underground transmission power cable. Its purpose is to gain knowleges of connect ing the CCPU and to show the merits as its method. There are many methods of connect ing CCPU, i.e, a conventional method, CIGRE method, interconnect ion between sheaths with grounding, and interconnect ion between sheaths without grounding. These methods will be compared in this paper.

• The Magazine of the IEIE
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• v.24 no.12
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• pp.52-68
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• 1997

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.39-46
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• 2005

This paper introduces a new At-speed Interconnect Test Controller (ASITC) that can detect and diagnose dynamic as well as static defects in an SoC. SoC is comprised of IEEE 1149.1 and P1500 wrapped cores which can be operated by multiple system clocks. In other to test such a complicated SoC, we designed a interface module for P1500 wrapped cores and the ASITC that makes it possible to detect interconnect delay faults during 1 system clock from launching to capturing the transition signal. The ASITC proposed requires less area overhead than other approaches and the operation was verified through the FPGA implementation

• The KIPS Transactions:PartA
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• v.10A no.4
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• pp.389-396
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• 2003

InfiniBand technology is being accepted as the future system interconnect to serve as the high-end enterprise fabric for cluster computing. This paper presents the design and implementation of the InfiniBand system interconnect, focusing on an InfiniBand host channel adapter (HCA) based on dual ARM9 processor cores The HCA is an SoC tailed KinCA which connects a host node onto the InfiniBand network both in hardware and in software. Since the ARM9 processor core does not provide necessary features for multiprocessor configuration, novel inter-processor communication and interrupt mechanisms between the two processors were designed and embedded within the KinCA chip. Kinch was fabricated as a 564-pin enhanced BGA (Bail Grid Array) device using 0.18${\mu}{\textrm}{m}$ CMOS technology Mounted on host nodes, it provides 10 Gbps outbound and inbound channels for transmit and receive, respectively, resulting in a high-performance cluster system.