• Title/Summary/Keyword: inter layer

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A Study on Improvement of Slurry Filter Efficiency in the CMP Process (CMP 공정에서 슬러리 필터의 효율 개선에 관한 연구)

  • Park, Sung-Woo;Seo, Yong-Jin;Seo, Sang-Yong;Lee, Woo-Sun;Kim, Chang-Il;Chang, Eui-Goo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.05b
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    • pp.34-37
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    • 2001
  • As the integrated circuit device shrinks to smaller dimensions, chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric (IMD) layer with free-defect. However, as the inter-metal dielectrics (IMD) layer gets thinner, micro-scratches are becoming as major defects. Micro-scratches are generated by agglomerated slurry, solidified and attached slurry in pipe line of slurry supply system. To prevent agglomerated slurry particle from inflow, we installed 0.5${\mu}m$ POU (point of use) filter, which is depth-type filter and has 80% filtering efficiency for the $1.0{\mu}m$ size particle. In this paper, we studied the relationship between defect generation and pad count to understand the exact efficiency of the slurry filtration, and to find out the appropriate pad usage. Our preliminary results showed that it is impossible to prevent defect-causing particles perfectly through the depth-type filter. Thus, we suggest that it is necessary to optimize the flow rate of slurry to overcome depth type filters weak-point, and to install the high spray of de-ionized Water (DIW) with high pressure.

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Aging effect of annealed oxide CMP slurry (열처리된 산화막 CMP 슬러리의 노화 현상)

  • Lee, Woo-Sun;Shin, Jae-Wook;Choi, Kwon-Woo;Ko, Pil-Ju;Seo, Yong-Jin
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.07a
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    • pp.335-338
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    • 2003
  • Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-layer dielectrics (ILD). Especially, defects such as micro-scratch lead to severe circuit failure which affect yield. CMP slurries can contain particles exceeding $1\;{\mu}m$ in size, which could cause micro-scratch on the wafer surface. In this paper, we have studied aging effect the of CMP sin as a function of particle size. We prepared and compared the self-developed silica slurry by adding of abrasives before and after annealing. As our preliminary experiment results, we could be obtained the relatively stable slurry characteristics comparable to original silica slurry in the slurry aging effect.

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Inter-Process Correlation Model based Hybrid Framework for Fault Diagnosis in Wireless Sensor Networks

  • Zafar, Amna;Akbar, Ali Hammad;Akram, Beenish Ayesha
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.13 no.2
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    • pp.536-564
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    • 2019
  • Soft faults are inherent in wireless sensor networks (WSNs) due to external and internal errors. The failure of processes in a protocol stack are caused by errors on various layers. In this work, impact of errors and channel misbehavior on process execution is investigated to provide an error classification mechanism. Considering implementation of WSN protocol stack, inter-process correlations of stacked and peer layer processes are modeled. The proposed model is realized through local and global decision trees for fault diagnosis. A hybrid framework is proposed to implement local decision tree on sensor nodes and global decision tree on diagnostic cluster head. Local decision tree is employed to diagnose critical failures due to errors in stacked processes at node level. Global decision tree, diagnoses critical failures due to errors in peer layer processes at network level. The proposed model has been analyzed using fault tree analysis. The framework implementation has been done in Castalia. Simulation results validate the inter-process correlation model-based fault diagnosis. The hybrid framework distributes processing load on sensor nodes and diagnostic cluster head in a decentralized way, reducing communication overhead.

Error Concealment Using Inter-layer Correlation for Scalable Video Coding

  • Park, Chun-Su;Wang, Tae-Shick;Ko, Sung-Jea
    • ETRI Journal
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    • v.29 no.3
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    • pp.390-392
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    • 2007
  • In this paper, we propose a new error concealment (EC) method using inter-layer correlation for scalable video coding. In the proposed method, the auxiliary motion vector (MV) and the auxiliary mode number (MN) of intra prediction are interleaved into the bitstream to recover the corrupted frame. In order to reduce the bit rate, the proposed method encodes the difference between the original and the predicted values of the MV and MN instead of the original values. Experimental results show that the proposed EC outperforms the conventional EC by 2.8 dB to 6.7 dB.

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Physical layer design of W-CDMA IMT-2000 system and performance analysis of key characteristics

  • 채명식;홍은기;최안나;구준모
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.23 no.5
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    • pp.1282-1290
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    • 1998
  • In this paper, the physical layer design of IMT-2000 system being developed by SK Telecom is introuduced. The outband signaling scheme and the two-pilot scheme are adopted for multimedia service and inter-cell asynchronous mode respectively. In addition, the synchronous transmission scheme is proposed to reduce the interference in the reverse link. The algorithm and simulation results of 'two-pilot scheme' for inter-cell asynchronous mode and 'reverse synchronous control' for synchronous transmission are presented.

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ILD(Inter-layer Dielectric) engineering for reduction of self-heating effort in poly-Si TFT (다결정 실리콘 박막 트렌지스터의 self-heating 효과를 감소시키기 위한 ILD 구조 개선)

  • Park, Soo-Jeong;Moon, Kook-Chul;Han, Min-Koo
    • Proceedings of the KIEE Conference
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    • 2002.11a
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    • pp.134-136
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    • 2002
  • 유리기판 위에서 제작된 다결정 실리콘 TFT(Thin Film Transistor) 에서는 열전도율이 낮은 실리콘 산화막 같은 물질이 사용되기 때문에 열에 대해서 낮은 임계점을 갖는다. 이로 인하여. 게이트와 드레인에 높은 전압이 걸리는 조건에서 동작시킬 경우에는 다결정 실리콘 TFT에서의 열화 현상이 두드러지게 나타나게 된다. 그러나, 열전도율이 실리콘 산화막(SiO2) 보다 열배 이상 높은 실리콘 질화막(SiNx)을 ILD(inter-layer dielectric) 재료로 사용했을 때 같은 스트레스 조건에서 다결정 실리콘의 신뢰성이 개선되는 것을 확인할 수 있었다.

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Electrical Coupling of Monolithic 3D Inverter Consisting of Junctionless FET (Junctionless FET로 구성된 적층형 3차원 인버터의 전기적 상호작용에 대한 연구)

  • Jang, Ho-Yeong;Kim, Kyung-won;Ahn, Tae-Jun;Yu, Yun Seop
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.10a
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    • pp.614-615
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    • 2016
  • I studied electrical coupling of monolithic 3D inverter(M3D-INV) consisting of Junctionless FET(JLFET). If the thickness of Inter Layer Dielectric (ILD) between top JLFET and bottom JLFET is less than 50nm, current-voltage characteristic of top JLFET is rapidly changed by the gate voltage of bottom JLFET. Therefore, you have to consider about the electrical interaction according to the thickness between top JLFET and bottom JLFET in M3D-INV.

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The effect of an EML sequence and an interlayer on the performance of the phosphorescent-fluorescent mixed WOLEDs

  • Baek, Heume-Il;Lee, Chang-Hee
    • 한국정보디스플레이학회:학술대회논문집
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    • 2008.10a
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    • pp.1215-1218
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    • 2008
  • We investigate the effect of a light emitting layer (EML) sequence and an interlayer on the performance of the phosphorescent-fluorescent mixed white organic light emitting diodes. Two types of phosphorescent-fluorescent mixed system were evaluated. The proper position of each primary color EML was crucial to obtain best performance in each system whereas the effect of an interlayer was found to be different in both systems.

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An Efficient Mode Decision Method for Fast Intra Encoding in the SVC Enhancement Layer (SVC 향상 계층의 빠른 인트라 부호화를 위한 효율적인 모드 결정 방법)

  • Cho, Mi-Sook;Kang, Jin-Mi;Chung, Ki-Dong
    • Journal of Korea Multimedia Society
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    • v.14 no.7
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    • pp.872-883
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    • 2011
  • SVC is an emerging video coding standard as an extension of H.264/AVC. This standard uses inter prediction, intra prediction and a new inter-layer prediction to improve coding performance of enhancement layers. However, it has high computational complexity. In this paper, we propose an efficient intra prediction mode decision method in the spatial enhancement layer to reduce the computational complexity. The proposed method consists of two phases. In the first phase, Intra_BL mode is selected using the RD cost of Intra_BL in advance. We exploit the fact that the RD cost and prediction mode are similar to those of neighbor macroblocks. In the second phase, we predict the enhancement layer mode using correlation between intra mode of enhancement layer and that of the base layer. Experimental results show that the proposed method could save from 48.15% to 56.32% in encoding time while degradation in video quality is negligible.