• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.3
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• pp.189-197
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• 2022

With the development of high-performance computing technology and the advancement of numerical model, it is possible to predict the better weather forecasting. The purpose of this paper is the performance improvement for the SCAM climate model for the model running time excluding the compilation time. Therefore, the model previously performed using the Intel Fortran Compiler was changed to PGI Fortran Compiler. To this end, we reconfigure system environment variables, reset compilation options, install dependencies SW and library, and modify source code. In addition, we proposed and applied the 'PGI Compile with OpenACC' method. As a result, when the compiler was changed from intel to PGI, it led to an improvement of 6.08% in running time and when the openACC method was applied, it led to an improvement of 43.05% in running time. This demonstrates that the PGI Compile with OpenACC method proposed in this paper leads to excellent performance.

• The Journal of Korean Institute of Next Generation Computing
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• v.13 no.4
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• pp.7-18
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• 2017

Electrical energy is one of the most important energy sources in modern society. Therefore, it is very important to control the supply and demand of electric power. However, the power consumption data needed to predict power demand may include the information about the private behavior of an individual, the analysis of which may raise privacy issues. In this paper, we propose a secure power demand forecasting method where regression analyses on power consumption data are conducted in a trusted execution environment provided by Intel SGX, keeping the power usage pattern of users private. We performed experiments using various regression equations and selected an equation which has the least error rate. We show that the average error rate of the proposed method is lower than those of the previous forecasting methods with privacy protection functionality.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2002.11a
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• pp.11-15
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• 2002

현재 공통평가기준을 이용하여 작성된 대부분의 파이어월과 VPN, 스마트 카드의 보호 프로파일의 기능요구사항에 영역분리기능이 포함되어 있다. 공통평가기준의 영역분리기능은 미국 국방성 운영체제 평가 기준인 TCSEC이 요구하는 보증수단에서 유래하였다. 8086프로세서는 리얼 모드라는 세그멘테이션 메커니즘을 처음으로 이용하여 향상된 메모리 주소관리를 제공하고 있으며, 80$\times$86은 리얼 모드이외에 보호모드를 제공하여 시스템 영역과 응용프로그램영역을 분리시킬 수 있는 메커니즘을 제공한다. 인텔 80$\times$86 프로세서의 구조적인 발전을 이용하여 구현된 Trusted OS는 링 상태(ring state)라고 알려져 있는 영역 분리기능을 제공하여 시스템의 영역을 응용 프로그램 영역으로부터 보호하는 메커니즘을 구현하고 보증하고 있다. 단 논문에서는 인텔 마이크로 프로세서 8086과 80$\times$86의 구조와 메모리 관리방법을 고찰하여 8086과 비교한 80$\times$86의 발전된 보호모드 메커니즘을 연구하여 시스템영역을 보호할 수 있는 영역분리 메커니즘을 연구하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.91-93
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• 2002

본 논문은 RISC CPU인 Intel StrongARM SA-1100을 기반으로 하는 실시간(Real-Time) 운영체제를 설계한 내용을 설명하고 있다. 본 논문에서 구현된 운영체제는 태스크들이 우선순위 기반으로 저리되는 선점형 스케줄링 방식을 채택함으로써 실기간 운영체제의 주요 특징인 시간 결정성(determinism)을 보장하도록 하였다. Intel StrongARM SA-1100은 고성능(High Performance), 저전력(Low Power)의 장점 때문에 모바일(Mobil) 환경에서 많이 사용되고 있다. 본 논문은 Intel StrongARM SA-1100 CPU를 타겟으로 시간 결정성이 보장되도록 멀티 태스킹(Multitasking)과 ITC(InterTasking Communication)를 설계하고 구현한 내용에 대해 설명하고 있다.

• Journal of Information Processing Systems
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• v.13 no.2
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• pp.204-214
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• 2017

Artificial intelligence, especially deep learning technology, is penetrating the majority of research areas, including the field of bioinformatics. However, deep learning has some limitations, such as the complexity of parameter tuning, architecture design, and so forth. In this study, we analyze these issues and challenges in regards to its applications in bioinformatics, particularly genomic analysis and medical image analytics, and give the corresponding approaches and solutions. Although these solutions are mostly rule of thumb, they can effectively handle the issues connected to training learning machines. As such, we explore the tendency of deep learning technology by examining several directions, such as automation, scalability, individuality, mobility, integration, and intelligence warehousing.

• Journal of the Korea Computer Industry Society
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• v.2 no.9
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• pp.1239-1244
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• 2001

The Virtual Interface Architecture (VIA) is usually suggested as a new standard high-performance communication of the cluster systems. However the VIA specification aims for platform independence, the current Intel VI Provider Library (VIPL) design favors systems with Intel architecture processors running the Windows operating system (OS). This paper aims for clarifying the guesstion problem of VIA and VIPL in the newtrul time of CPU Architecture and OS further more, It suggests the solution aiming the communication in the other CPU or OS

• The Journal of Information Systems
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• v.14 no.3
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• pp.97-104
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• 2005

The paper proposes an implementation architecture of DiffServ-over-MPLS traffic engineering (TE) on Intel IXP2400 network processor using Intel IXA SDK 4.0 Framework. Program architecture and functions are described. Also fast and scalable range-match classification scheme is proposed for DiffServ-over-MPLS TE that has been integrated with functional blocks from Intel Microblocks library. Performance test shows that application can process packets at approximate data rate of 3.5 Gbps. The proposed implementation architecture of DiffServ-over-MPLS TE on Network processor can provide guaranteed QoS on high-speed next generation Internet, while being flexible and easily modifiable.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2684-2686
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• 2001

In order to utilize cache in multiprocessor system, cache coherence problem must be handled. Central directory scheme is one of hardware-assisted cache coherence solutions. The goal of this paper was not only to propose some special methods needed to apply central directory scheme to the specific multiprocessor system based on Intel486 microprocessors but also to design central directory unit for cache coherence of the target system. The problems of arbitrating several requests from processors, storing the cache information, and generating control signals for cache line fill and snoop cycle were solved.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.10a
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• pp.301-302
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• 2006

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.10a
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• pp.299-300
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• 2006