• 제목/요약/키워드: integrator

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Optimal PID Control for Temperature Control of Chiller Equipment (칠러장비의 온도제어를 위한 최적 PID 제어)

  • Park, Young-shin;Lee, Dongju
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.45 no.3
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    • pp.131-138
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    • 2022
  • The demand for chiller equipment that keeps each machine at a constant temperature to maintain the best possible condition is growing rapidly. PID (Proportional Integral Derivation) control is a popular temperature control method. The error, which is the difference between the desired target value and the current system output value, is calculated and used as an input to the system using a proportional, integrator, and differentiator. Through such a closed-loop configuration, a desired final output value of the system can be reached using only the target value and the feedback signal. Furthermore, various temperature control methods have been devised as the control performance of various high-performance equipment becomes important. Therefore, it is necessary to design for accurate data-driven temperature control for chiller equipment. In this research, support vector regression is applied to the classic PID control for accurate temperature control. Simulated annealing is applied to find optimal PID parameters. The results of the proposed control method show fast and effective control performance for chiller equipment.

Inhibition Effects of Persicaria amphibia (L.) Delarbre on Oxidative DNA Damage via ATM/Chk2/p53 pathway

  • So-Yeon Han;Hye-Jeong Park;Jeong-Yong Park;Seo-Hyun Yun;Mi-Ji Noh;Soo-Yeon Kim;Tae-Won Jang;Jae-Ho Park
    • Proceedings of the Plant Resources Society of Korea Conference
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    • 2021.04a
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    • pp.52-52
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    • 2021
  • Persicaria amphibia as an England native plant, is a rhizomatous perennial, one of the rather amphibious plants. Its aquatic form contains water-soluble sugars, starch, and protein. P. amphibia have up to 18% tannins in stems and rhizomes. Previous studies have confirmed the anti-inflammatory activity of live bacteria roots, but no studies on bioactivity are known. DNA damage responses (DDRs) pathways are considered a crucial factor affecting the alleviation of cellular damage. The ataxia-telangiectasia mutated and Rad3 related (ATM) and checkpoint kinase 2 (Chk2) pathways are the main pathways of DNA damage response. Also, p53 is a key integrator of cellular response to oxidative DNA damage, contributing repair, or leading transcription including apoptosis. In the present study, we conducted an investigation into the inhibitory effects of P. amphibia on oxidative DNA damage for confirming potential to complementary medicine and therapies. In conclusion, P. amphibia can provide protective effects against double-stranded DNA break (DSB) caused by oxidative DNA damage.

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Improved Programmable LPF Flux Estimator with Synchronous Angular Speed Error Compensator for Sensorless Control of Induction Motors (유도 전동기 센서리스 제어를 위한 동기 각속도 오차 보상기를 갖는 향상된 Programmable LPF 자속 추정기)

  • Lee, Sang-Soo;Park, Byoung-Gun;Kim, Rae-Young;Hyun, Dong-Seok
    • The Transactions of the Korean Institute of Power Electronics
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    • v.18 no.3
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    • pp.232-239
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    • 2013
  • This paper proposes an improved stator flux estimator through ensuring conventional PLPF to act as a pure integrator for sensorless control of induction motors. Conventional PLPF uses the estimated synchronous speed as a cut-off frequency and has the gain and phase compensators. The gain and phase compensators are determined on the assumption that the estimated synchronous angular speed is coincident with the real speed. Therefore, if the synchronous angular speed is not same as the real speed, the gain and phase compensation will not be appropriate. To overcome the problem of conventional PLPF, this paper analyzes the relationship between the synchronous speed error and the phase lag error of the stator flux. Based on the analysis, this paper proposes the synchronous speed error compensation scheme. To achieve a start-up without speed sensor, the current model is used as the stator flux estimator at the standstill. When the motor starts up, the current model should be switched into the voltage model. So a stable transition between the voltage model and the current model is required. This paper proposes the simple transition method which determines the initial values of the voltage model and the current model at the transition moment. The validity of the proposed schemes is proved through the simulation results and the experimental results.

New Fuzzy Controller for High Performance of IPMSM Drive (IPMSM 드라이브의 고성능 제어를 위한 새로운 퍼지제어기)

  • 이정철;이홍균;김종관;정동화
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.40 no.3
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    • pp.199-207
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    • 2003
  • This paper is proposed new fuzzy controller for high performance of interior permanent magnet synchronous motor(IPMSM) drive. New fuzzy controller take out appropriate amounts of accumulated control input according to fuzzily described situations in addition to the incremental control input calculated by conventional direct fuzzy controller The structures of the proposed controller is motivated by the problems of direct fuzzy controller. The direct controller generally give inevitable overshoot when one tries to reduce rise time of response especially when a system of order higher than one is under consideration. The undesirable characteristics of the direct fuzzy controller are caused by integrating operation of the controller, even though the Integrator itself is introduced to overcome steady state error in response. Proposed controller fuzzily clear out integrated quantities acrording to situation. This paper attempts to provide a thorough comparative insight into the behavior of IPMSM drive with direct and new fuzzy speed controller. The validity of new fuzzy speed controller is confirmed by response results for IPMSM drive system.

A Concept of Multi-Layered Database for the Maintenance and Management of Bridges (교량의 유지관리를 위한 멀티레이어 데이터베이스 개념)

  • Kim, Bong-Geun;Yi, Jin-Hoon;Lee, Sang-Ho
    • Journal of the Computational Structural Engineering Institute of Korea
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    • v.20 no.3
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    • pp.393-404
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    • 2007
  • A concept of multi-layered database is proposed for the integrated operation of bridge information in this study. The multi-layered database is a logically integrated database composed of standardized information layers. The standardized information layers represent the data sets that can be unified, and they are defined by standardized information models. Classification system of bridge component was used as a basis of the multi-layered database, and code system based on the classification system was employed as a key integrator to manipulate the distributed data located on the different information layers. In addition, data level indicating priorities of information layers was defined to support strategic planning of the multi-layered database construction. As a proof of concept, a prototype of multi-layered database for object-oriented 3-D shape information and structural calculation document was built. Data consistency check of the semantically same data in the two different information layer was demonstrated, It is expected that the proposed concept can assure the integrity and consistency of information in the bridge information management.

An 8-Gb/s/channel Asymmetric 4-PAM Transceiver with an Adaptive Pre-emphasis for Memory Interface (메모리 인터페이스를 위한 적응형 프리엠퍼시스를 가지는 8-Gb/s/채널 비균형 4-레벨 펄스진폭변조 입출력회로)

  • Jang, Young-Chan;Jun, Young-Hyun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.8
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    • pp.71-78
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    • 2009
  • An 8${\times}$8-Gb/s/channel 4-PAM transceiver was designed for high speed memory applications by using 70nm DRAM process with 1.35V supply. An asymmetric 4-PAM signaling scheme is proposed to increase the voltage and time margin of upper and lower eyes in 3-class eye opening. A mathematical basis shows that this scheme statistically reduces 33% of reference noise effect in a receiver. Also, an adaptive pre-emphasis scheme, which utilizes a lone-bit pulse with integrator at the receiver, is introduced to reduce ISI for a simple DRAM channel. In this scheme, an integrating clock timing calibration by using a pre-determined pattern is proposed for the optimum ISI measurement.

An Effect on the Audit Quality and Customer Satisfaction by the Service Quality of Information System Audit (정보시스템감리의 서비스품질요인이 감리품질과 고객만족에 미치는 영향)

  • Kim DongSoo;Kim Hyunsoo;Ahn Yeonshick
    • The KIPS Transactions:PartD
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    • v.11D no.7 s.96
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    • pp.1467-1476
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    • 2004
  • The importance and demand about IS(information system) audit we increasing to raise quality of IS and prevention of the IS risk and dysfunction. Technology and system research for the substantiality and raising reliability of IS audit are continuously performed. But, there are misunderstanding of audit clients about IS audit, insufficiency of auditor's ability and misunderstanding of new technology and target business area. Therefore, is not getting trust from client or system integrator because service quality of IS audit is weak relatively. This study aims at survey correlation between audit service quality factor and audit quality, between audit quality and customer satisfaction. The results of this study are as follow. Auditor's ability, correspondence has a significant effect on audit quality, also audit quality on audit satisfaction, and Auditor`s ability, reliability has a significant effect on audit satisfaction.

A Study on the Design and Validation of Switching Mechanism in Hot Bench System-Switch Mechanism Computer Environment (HBS-SWMC 환경에서의 전환장치 설계 및 검증에 관한 연구)

  • Kim, Chong-Sup;Cho, In-Je;Ahn, Jong-Min;Lee, Dong-Kyu;Park, Sang-Seon;Park, Sung-Han
    • Journal of Institute of Control, Robotics and Systems
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    • v.14 no.7
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    • pp.711-719
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    • 2008
  • Although non-real time simulation and pilot based evaluations are available for the development of flight control computer prior to real flight tests, there are still many risky factors. The control law designed for prototype aircraft often leads to degraded performance from the initial design objectives, therefore, the proper evaluation methods should be applied such that flight control law designed can be verified in real flight environment. The one proposed in this paper is IFS(In-Flight Simulator). Currently, this system has been implemented into the F-18 HARV(High Angle of Attack Research Vehicle), SU-27 and F-16 VISTA(Variable stability. In flight Simulation Test Aircraft) programs. This paper addresses the concept of switching mechanism for FLCC(Flight Control Computer)-SWMC(Switching Mechanism Computer) using 1553B communication based on flight control law of advanced supersonic trainer. And, the fader logic of TFS(Transient Free Switch) and stand-by mode of reset '0' type are designed to reduce abrupt transient and minimize the integrator effect in pitch axis control law. It hans been turned out from the pilot evaluation in real time that the aircraft is controllable during the inter-conversion process through the flight control computer, and level 1 handling qualities are guaranteed. In addition, flight safety is maintained with an acceptable transient response during aggressive maneuver performed in severe flight conditions.

Verification of Real-time Hybrid Test System using RC Pier Model (RC교각을 이용한 실시간 하이브리드 실험 시스템의 적용성 연구)

  • Lee, Jinhaeng;Park, Minseok;Chae, Yunbyeong;Kim, Chul-Young
    • Journal of the Earthquake Engineering Society of Korea
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    • v.22 no.4
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    • pp.253-259
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    • 2018
  • Structure behaviors resulting from an earthquake are experimentally simulated mainly through a shaking table test. As for large-scale structures, however, size effects over a miniature may make it difficult to assess actual behaviors properly. To address this problem, research on the hybrid simulation is being conducted actively. This method is to implement numerical analysis on framework members that affect the general behavior of the structure dominantly through an actual scale experiment and on the rest parts by applying the substructuring technique. However, existing studies on hybrid simulation focus mainly on Slow experimental methods, which are disadvantageous in that it is unable to assess behaviors close to the actual level if material properties change depending on the speed or the influence of inertial force is significant. The present study aims to establish a Real-time hybrid simulation system capable of excitation based on the actual time history and to verify its performance and applicability. The hybrid simulation system built up in this study utilizes the ATS Compensator system, CR integrator, etc. in order to make the target displacement the same with the measured displacement on the basis of MATLAB/Simulink. The target structure was a 2-span bridge and an RC pier to support it was produced as an experimental model in order for the shaking table test and Slow and Real-time hybrid simulations. Behaviors that result from the earthquake of El Centro were examined, and the results were analyzed comparatively. In comparison with the results of the shaking table test, the Real-time hybrid simulation produced more similar maximum displacement and vibration behaviors than the Slow hybrid simulation. Hence, it is thought that the Real-time hybrid simulation proposed in this study can be utilized usefully in seismic capacity assessment of structural systems such as RC pier that are highly non-linear and time-dependent.

A 1.8 V 0.18-μm 1 GHz CMOS Fast-Lock Phase-Locked Loop using a Frequency-to-Digital Converter

  • Lee, Kwang-Hun;Jang, Young-Chan
    • Journal of information and communication convergence engineering
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    • v.10 no.2
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    • pp.187-193
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    • 2012
  • A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.