• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.13 no.4
• /
• pp.85-98
• /
• 2003

Computational power of IC chip is improved day after day producing IC chips holding co-processor continuously. Also a lot of wireless terminals which IC chip embedded in are produced in order to provide simple and various services in the wireless terminal market. However it is difficult to apply the key distribution protocol under wired communication environment to wireless communication environment. Because the computational power of co-processor embedded in IC chip under wireless communication environment is less than that under wired communication environment. In this paper, we propose the hey distribution protocol appropriate for wireless communication environment which diminishes the computational burden of server and client by using co-processor that performs cryptographic operations and makes up for the restrictive computational power of terminal. And our proposal is satisfied with the security requirements that are not provided in existing key distribution protocol.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.26 no.10
• /
• pp.1537-1544
• /
• 2022

When designing chip, it considers design specification, timing problem, and clock synchronization on place & route (P&R) process. P&R process is complicated because of considering various factors. Chip uses clock tree synthesis (CTS) to reduce clock path delay. The purpose of this study is to examine shallow-CTS algorithm for checking clock tree synthesizable. Using open source Parser-Verilog, register transfer level (RTL) synthesizable Verilog file is parsed and it uses Pre-CTS and Post-CTS process that is included shallow-CTS. Based on longest clock path in the Pre-CTS and Post-CTS stages, the standard deviation before and after buffer insertion is compared and analyzed for the accuracy of CTS. In this paper, It is expected that the cost and time problem could be reduced by providing a pre-clock tree synthesis verification method at the RTL level without confirming the CTS result using the time-consuming licensed EDA tool.

• Tunnel and Underground Space
• /
• v.32 no.6
• /
• pp.345-352
• /
• 2022

The existing NATM (New Austrian Tunneling Method) has induced civil compliants due to blasting vibration and noise. Machanized excavation methods such as TBM (Tunnel Boring Machine) are being adopted in the planning and construction of tunneling projects. Shield TBM method is composed of repetition processes of TBM excavation and segment installation, the machine has to be stopped during the later process. Consecutive excavation technology using helical segment is under developing to minimize the stoppage time. The modification of thrust jacks and module are planned to ensure the advance force acting on the inclined surface of helical segment. Also, the integrated system design of hydraulic circuit will be remodeled. This means that the system deactivate the jacks on the installing segment while the others automatically act the thrusting forces on the existing segments. This report briefly introduces the mechanical research part of the current consecutive excavation technological development project of TBM.

• Journal of IKEEE
• /
• v.26 no.4
• /
• pp.722-727
• /
• 2022

In this paper, we present the design and characterization of a power amplifier (PA) monolithic microwave integrated circuit (MMIC) in the X-band. The device is designed using a 0.25 ㎛ gate length AlGaN/GaN high electron mobility transistor (HEMT) on SiC process. The developed X-band AlGaN/GaN power amplifier MMIC achieves small signal gain of over 21.6 dB and output power more than 46.11 dBm (40.83 W) in the entire band of 9 GHz to 10 GHz. Its power added efficiency (PAE) is 43.09% ~ 44.47% and the chip dimensions are 3.6 mm × 4.3 mm. The generated output power density is 2.69 W/mm². It seems that the developed AlGaN/GaN power amplifier MMIC could be applicable to various X-band radar systems operating X-band.

• Journal of the Korea Institute of Military Science and Technology
• /
• v.26 no.3
• /
• pp.227-233
• /
• 2023

In this paper, to substitute the existing TWTA(Travailing Wave Tube Amplifier) component in small radar system, we developed the Ku band SSPA(Solid-State Power Amplifier) based on the fabrication of power MMIC (Monolithic Microwave Integrated Circuit) chips. For the development of the 500 W SSPA, the 40 W-grade power MMIC was designed by ADS(Advanced Design System) at Keysight company with UMS GH015 library, and was processed by UMS foundry service. And 70 W main power modules were achieved the 2-way T-junction combiner method by using the 40 W-grade power MMICs. Finally, the 500 W SSPA was fabricated by the wave guide type power divider between the drive power amplifier and power modules, and power combiner with same type between power modules and output port. The electrical properties of this SSPA had 504 W output power, -58.11 dBc spurious, 1.74 °/us phase variation, and -143 dBm/Hz noise level.

• Journal of IKEEE
• /
• v.28 no.1
• /
• pp.33-37
• /
• 2024

In this paper, we report the design and the measurement of a X-band low noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) using a 0.25 ㎛ gate length microstrip GaN-on-SiC high electron mobility transistor (HEMT) technology. The developed X-band GaN-based LNA MMIC achieves small signal gain of 22.75 dB ~ 25.14 dB and noise figure of 1.84 dB ~ 1.94 dB in the desired band of 9 GHz to 10 GHz. Input and output return loss values are -11.36 dB ~ -24.49 dB and -11.11 dB ~ -17.68 dB, respectively. The LNA MMIC can withstand 40 dBm (10 W) input power without performance degradation. The chip dimensions are 3.67 mm × 1.15 mm. The developed GaN-based LNA MMIC is applicable to various X-band applications.

• Journal of IKEEE
• /
• v.28 no.3
• /
• pp.337-341
• /
• 2024

As the production process for silicon-based integrated circuits approaches physical limits, a lot of attention is focused on the new semiconductor materials to overcome these problems. Carbon NanoTubes(CNTs) are attracting a lot of interest as one of the most competitive materials with excellent electrical transport and scaling properties, and CNTFETs using CNTs are gaining popularity as next-generation semiconductor devices. However, since the technology to place CNTs in a certain direction and interval on the wafer is not yet mature enough, it is difficult to construct all necessary circuits with CNTFET only. So, there is increasing interest in a hybrid configuration using MOSFET and CNTFET together. Because SRAM plays a role as a cache in microprocessors and is a critical circuit block influencing microprocessor performance, research to implement existing SRAM in a hybrid form is steadily progressing. Therefore, in this paper, we will explain the design method of hybrid 8T SRAM based on the existing hybrid 6T SRAM and discuss the performance difference between the two circuits.

• Journal of Intelligence and Information Systems
• /
• v.20 no.2
• /
• pp.163-178
• /
• 2014

Following research proposes "Virtualization of Smart Cards (ViSCa)" which is a security system that aims to provide a multi-device platform for the deployment of services that require a strong security protocol, both for the access & authentication and execution of its applications and focuses on analyzing Virtualization of Smart Cards (ViSCa) platform-based mobile payment service by comparing with other similar cases. At the present day, the appearance of new ICT, the diffusion of new user devices (such as smartphones, tablet PC, and so on) and the growth of internet penetration rate are creating many world-shaking services yet in the most of these applications' private information has to be shared, which means that security breaches and illegal access to that information are real threats that have to be solved. Also mobile payment service is, one of the innovative services, has same issues which are real threats for users because mobile payment service sometimes requires user identification, an authentication procedure and confidential data sharing. Thus, an extra layer of security is needed in their communication and execution protocols. The Virtualization of Smart Cards (ViSCa), concept is a holistic approach and centralized management for a security system that pursues to provide a ubiquitous multi-device platform for the arrangement of mobile payment services that demand a powerful security protocol, both for the access & authentication and execution of its applications. In this sense, Virtualization of Smart Cards (ViSCa) offers full interoperability and full access from any user device without any loss of security. The concept prevents possible attacks by third parties, guaranteeing the confidentiality of personal data, bank accounts or private financial information. The Virtualization of Smart Cards (ViSCa) concept is split in two different phases: the execution of the user authentication protocol on the user device and the cloud architecture that executes the secure application. Thus, the secure service access is guaranteed at anytime, anywhere and through any device supporting previously required security mechanisms. The security level is improved by using virtualization technology in the cloud. This virtualization technology is used terminal virtualization to virtualize smart card hardware and thrive to manage virtualized smart cards as a whole, through mobile cloud technology in Virtualization of Smart Cards (ViSCa) platform-based mobile payment service. This entire process is referred to as Smart Card as a Service (SCaaS). Virtualization of Smart Cards (ViSCa) platform-based mobile payment service virtualizes smart card, which is used as payment mean, and loads it in to the mobile cloud. Authentication takes place through application and helps log on to mobile cloud and chooses one of virtualized smart card as a payment method. To decide the scope of the research, which is comparing Virtualization of Smart Cards (ViSCa) platform-based mobile payment service with other similar cases, we categorized the prior researches' mobile payment service groups into distinct feature and service type. Both groups store credit card's data in the mobile device and settle the payment process at the offline market. By the location where the electronic financial transaction information (data) is stored, the groups can be categorized into two main service types. First is "App Method" which loads the data in the server connected to the application. Second "Mobile Card Method" stores its data in the Integrated Circuit (IC) chip, which holds financial transaction data, which is inbuilt in the mobile device secure element (SE). Through prior researches on accept factors of mobile payment service and its market environment, we came up with six key factors of comparative analysis which are economic, generality, security, convenience(ease of use), applicability and efficiency. Within the chosen group, we compared and analyzed the selected cases and Virtualization of Smart Cards (ViSCa) platform-based mobile payment service.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.9
• /
• pp.25-33
• /
• 2007

In this paper, the high isolation and wideband 94 GHz MIMIC(Millimeter-wave Monolithic Integrated Circuit) single balanced cascode mixer was designed and fabricated. Also, we designed and fabricated a 3 dB tandem coupler which has a high isolation and wideband characteristic. The single balanced resistive mixer which does not require an external IF balun was designed using the 0.1 ${\mu}m$ InGaAs/InAlAs/GaAs metamorphic HEMT(High Electron Mobility Transistor). The DC characteristics of MHEMT's are 665 mA/mm of drain current density, 691 mS/mm of maximum transconductance. The current gain cut-off frequency($f_T$) is 189 GHz and the maximum oscillation frequency($f_{max}$) is 334 GHz. A 94 GHz single balanced cascode mixer was fabricated using our 0.1 ${\mu}m$ MHEMT MIMIC process. From the measurements, the fabricated couplers showed wideband characteristics. The conversion loss of single balanced cascode mixer was 9.8 dB at an LO power of 10.9 dBm. The LO to RF isolation of single balanced cascode mixer was 29.5 dB at 94 GHz. We obtained in this study a higher LO-RF isolation compared to some other single balanced mixers.

• Journal of the Korea Institute of Building Construction
• /
• v.22 no.6
• /
• pp.651-662
• /
• 2022

The electrochemical impedance spectroscopy(EIS) method was used to evaluate the concrete deterioration process related to chloride-induced steel corrosion with various corrosion levels(initiation, rust propagation and acceleration periods). The impressed current technique, with four total current levels of 0C, 13C, 65C and 130C, was used to accelerate steel corrosion in concrete cylinder samples with w/c ratio of 0.4, 0.5, and 0.6, immersed in a 0.5M NaCl solution. A series of EIS measurements was performed to monitor concrete deterioration during the accelerated corrosion test in this study. Some critical parameters of the equivalent circuit were obtained through the EIS analysis. It was observed that the charge transfer resistance(R_c) dropped sharply as the impressed current increased from 0C to 13C, indicating a value of approximately 10kΩcm². However, the sensitivity of R_c significantly decreased when the impressed current was further increased from 13C to 130C after corrosion of steel had been initiated. Meanwhile, the double-layer capacitance value(C_dl) linearly increased from 50×10^-6μF/cm² to 250×10^-6μF/cm² as the impressed current in creased from 0C to 130C. The results in this study showed that monitoring C_dl is an effective measurement parameter for evaluating the progress of internal concrete damages(de-bonding between steel and concrete, micro-cracks, and surface-breaking cracks) induced by steel corrosion. The findings of this study provide a fundamental basis for developing an embedded sensor and signal interpretation method for monitoring concrete deterioration due to steel corrosion at various corrosion levels.