• 제목/요약/키워드: integer multiplication

검색결과 52건 처리시간 0.024초

복소수의 대수적 정수환 근사화를 이용한 이산 후리에 변환 (The Discrete Fourier Transform Using the Complex Approximations of the Ring of Algebraic Integer)

  • 김덕현;김재공
    • 전자공학회논문지B
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    • 제30B권9호
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    • pp.18-26
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    • 1993
  • This paper presents a multiplier free technique for the complex DFT by rotations and additions based on the complex approximation of the ring of algebraic integers. Speeding-up the computation time and reducing the dynamic range growth has been achieved by the elimination of multiplication. Moreover the DFT of no twiddle factor quantization errors is possible. Numerical examples are given to prove the algorithm and the applicable size of the DFT is 16 has been concluded.

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연산자로서의 유리수 체계의 구성에 관한 연구

  • 정영우;김부윤
    • East Asian mathematical journal
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    • 제28권2호
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    • pp.135-158
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    • 2012
  • The ideals of the rings of integers are used to induce rational number system as operators(=group homomorphisms). We modify this inducing method to be effective in teaching rational numbers in secondary school. Indeed, this modification provides a nice model for explaining the equality property to define addition and multiplication of rational numbers. Also this will give some explicit ideas for students to understand the concept of 'field' efficiently comparing with the integer number system.

ARTIN SYMBOLS OVER IMAGINARY QUADRATIC FIELDS

  • Dong Sung Yoon
    • East Asian mathematical journal
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    • 제40권1호
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    • pp.95-107
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    • 2024
  • Let K be an imaginary quadratic field with ring of integers 𝓞K and N be a positive integer. By K(N) we mean the ray class field of K modulo N𝓞K. In this paper, for each prime p of K relatively prime to N𝓞K we explicitly describe the action of the Artin symbol (${\frac{K_{(N)}/K}{p}}$) on special values of modular functions of level N. Furthermore, we extend the Kronecker congruence relation for the elliptic modular function j to some modular functions of higher level.

ECC(Elliptic Curve Crptographics) 기반의 보안프로세서를 위한 스칼라 곱셈기의 FPGA 구현 (Design and FPGA Implementation of the Scalar Multiplier for a CryptoProcessor based on ECC(Elliptic Curve Cryptographics))

  • 최선준;황정태;김영철
    • 한국정보처리학회:학술대회논문집
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    • 한국정보처리학회 2005년도 춘계학술발표대회
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    • pp.1071-1074
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    • 2005
  • The ECC(Elliptic Curve Cryptogrphics), one of the representative Public Key encryption algorithms, is used in Digital Signature, Encryption, Decryption and Key exchange etc. The key operation of an Elliptic curve cryptosystem is a scalar multiplication, hence the design of a scalar multiplier is the core of this paper. Although an Integer operation is computed in infinite field, the scalar multiplication is computed in finite field through adding points on Elliptic curve. In this paper, we implemented scalar multiplier in Elliptic curve based on the finite field $GF(2^{163})$. And we verified it on the Embedded digital system using Xilinx FPGA connected to an EISC MCU(Agent 2000). If my design is made as a chip, the performance of scalar multiplier applied to Samsung $0.35\;{\mu}m$ Phantom Cell Library is expected to process at the rate of 8kbps and satisfy to make up an encryption processor for the Embedded digital information home system.

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다단계제조공정의 품질개선을 위한 종속대안선택 근사해법 (Heuristic Algorithm for Selecting Mutually Dependent Qualify Improvement Alternatives of Multi-Stage Manufacturing Process)

  • 조남호
    • 산업경영시스템학회지
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    • 제11권18호
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    • pp.7-15
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    • 1988
  • This study is concerned with selecting mutually dependent quality improvement alternatives with resource constraints. These qualify improvement alternatives art different fro the tradition at alternatives which are independent from each other. In other words, selection of any improvement alternative requires other related specific improvement. Also the overall product quality in a multi stage manufacturing process is characterized by a complex multiplication method rather than a simple addition method which dose not allow to solve a linear knapsack problem despite its popularity in the traditional study. This study suggests a non-linear integer programming model for selecting mutually dependent quality improvement alternatives in multi-stage manufacturing process. In order to apply the model to selecting alternatives. This study also suggests a heuristic mode1 based on a dynamic programming model which is more practical than the non-linear integer programming model. The logic of the heuristic model enables 1) to estimate improvement effectiveness values on all improvement alternatives specifically defined for this study. 2) to arrange the effectiveness values in a descending order, and 3) to select the best one among the alternatives based on their forward and backward linkage relationships. This process repeats to selects other best alternatives within the resource constraints. This process is presented in a Computer programming in Appendix A. Alsc a numerical example of model application is presented in Chapter 4.

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An Efficient Architecture Design of Low Complexity in Quantization of H.264/AVC

  • Lama, Ramesh Kumar;Yun, Jung-Hyun;Kwon, Goo-Rak
    • 한국멀티미디어학회논문지
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    • 제14권10호
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    • pp.1238-1242
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    • 2011
  • An efficient architecture for the reduction of complexity in forward quantization of H.264/AVC is presented in this paper. Since the multiplication operation in forward quantization plays crucial role in complexity of algorithm. More efficient quantization architecture with simplified high speed multiplier is proposed. It uses the modification of the quantization operation and the high speed multiplier is applied for simplification of quantization process.

H.264/AVC 압축 도메인에서의 프레임 resizing 방법 (Frame resizing scheme in H.264/AVC compressed domain)

  • 오형석;김원하
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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    • pp.145-147
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    • 2006
  • Image resizing is to change an image size by upsampling or downsampling of a digital image. Most still images and video frames are given in a compressed domain on digital media. Image resizing of a compressed image can be performed in a spatial domain via decompression or recompression. In general, resizing of a compressed image in a compressed domain is much faster than that in a spatial domain. In this paper, we propose an approach to resize images in the integer discrete cosine transform (DCT) domain, which exploits the multiplication-convolution property of DCT.

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Simple Countermeasure to Cryptanalysis against Unified ECC Codes

  • Baek, Yoo-Jin
    • Journal of Communications and Networks
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    • 제12권1호
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    • pp.1-4
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    • 2010
  • As a countermeasure to simple power attack, the unified point addition codes for the elliptic curve cryptosystem were introduced. However, some authors proposed a different kind of power attacks to the codes. This power attack uses the observation that some internal operations in the codes behave differently for addition and doubling. In this paper, we propose a new countermeasure against such an attack. The basic idea of the new countermeasure is that, if one of the input points of the codes is transformed to an equivalent point over the underlying finite field, then the code will behave in the same manner for addition and doubling. The new countermeasure is highly efficient in that it only requires 27(n-1)/3 extra ordinary integer subtractions (in average) for the whole n-bit scalar multiplication. The timing analysis of the proposed countermeasure is also presented to confirm its SPA resistance.

컨텐츠 보호를 위한 DTCP용 타원곡선 암호(ECC) 연산기의 구현 (Design of a ECC arithmetic engine for Digital Transmission Contents Protection (DTCP))

  • 김의석;정용진
    • 한국통신학회논문지
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    • 제30권3C호
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    • pp.176-184
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    • 2005
  • 본 논문에서는 디지털 컨텐츠 보호를 위해 표준으로 제정된 DTCP(Digital Transmission Contents Protection)용 타원 곡선 암호(ECC) 연산기의 구현에 대해 기술한다. 기존의 시스템이 유한체 GF(2/sup m/)를 사용하는 것과는 달리 DTCP에서는 소수체인 GF(p)에서 타원 곡선을 정의하여 인증 및 키 교환을 위해 ECC 암호 알고리즘을 사용하고 있다. 본 논문에서는 ECC 알고리즘의 핵심 연산인 GF(p) 상에서의 스칼라 곱셈 연산기를 구현하였으며, 이 중 가장 많은 시간과 자원을 필요로 하는 나눗셈 연산을 제거하기 위하여 투영 좌표 변환 방법을 이용하였다. 또한, 효율적인 모듈러 곱셈 연산을 위하여 몽고메리 알고리즘을 이용하였으며, 곱셈기의 처리 속도를 빠르게 하기 위해 CSA(Carry Save Adder)와 4-레벨의 CLA(Carry Lookahead Adder)를 사용하였다. 본 논문에서 설계한 스칼라 곱셈기는 삼성전자 0.18 un CMOS 라이브러리를 이용하여 합성하였을 경우 64,559 게이트의 크기에 최대 98 MHz까지 동작이 가능하며 이 때 데이터 처리속도는 29.6 kbps로 160-blt 프레임당 5.4 ms 걸린다. 본 성능은 실시간 환경에서 DTCP를 위한 디지털 서명, 암호화 및 복호화, 그리고 키 교환 등에 효율적으로 적용될 수 있다.

Design and Analysis of Efficient Parallel Hardware Prime Generators

  • Kim, Dong Kyue;Choi, Piljoo;Lee, Mun-Kyu;Park, Heejin
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제16권5호
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    • pp.564-581
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    • 2016
  • We present an efficient hardware prime generator that generates a prime p by combining trial division and Fermat test in parallel. Since the execution time of this parallel combination is greatly influenced by the number k of the smallest odd primes used in the trial division, it is important to determine the optimal k to create the fastest parallel combination. We present probabilistic analysis to determine the optimal k and to estimate the expected running time for the parallel combination. Our analysis is conducted in two stages. First, we roughly narrow the range of optimal k by using the expected values for the random variables used in the analysis. Second, we precisely determine the optimal k by using the exact probability distribution of the random variables. Our experiments show that the optimal k and the expected running time determined by our analysis are precise and accurate. Furthermore, we generalize our analysis and propose a guideline for a designer of a hardware prime generator to determine the optimal k by simply calculating the ratio of M to D, where M and D are the measured running times of a modular multiplication and an integer division, respectively.