• Journal of the Korea Society of Computer and Information
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• v.3 no.1
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• pp.125-148
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• 1998

The use of shaping mechanism, realized by means of a leaky bucket based algorithm on input traffic of an ATM network allows to achieve higher utilization of network resources, and to guarantee the quality of service requested by the users. The functionalities of the shaping mechanism based on leaky bucket, are characterized by the token pool sire and by input queue size. In this paper we have analyzed, using simulations, the effect on the quality of service in ATM network of leaky bucket algorithm when shaper parameters described above are changed.

• Journal of the Korean Society for Precision Engineering
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• v.25 no.4
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• pp.26-31
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• 2008

본 논문은 정밀 위치결정 시스템의 잔류진동을 효과적으로 제거할 수 있는 입력성형기법을 소개하고, 실시간 입력성형기법을 적용하는 방법을 설명하였다. 또한 두 가지 응용 분야에 대한 실험결과를 바탕으로 입력성형기법의 성능을 고찰하였다. 일반적으로 입력성형기법은 정밀 위치결정 시스템에 대해 동작 완료시간을 단축시키는 효과가 있을 뿐만 아니라 위치결정 정밀도를 향상시키는 효과가 있다. 그리고 되먹임제어 방법에 비해 적용방법도 간단하며 저렴하게 구성할 수 있다는 장점이 있으므로 많은 정밀 위치결정 시스템에 유용할 것으로 생각된다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.5
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• pp.597-604
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• 1986

This paper describes various mismatch phenomena in differential pulse code modulation (DPCM) coding, such as the mismatch effects of probability density functin(pdf), signal variance, and correlation. At a high transmission rate(i.e., above 32 kbits/s), the performance of DPCM can be improved by matching the pdf shape between the input signal and the quantizer. However, the same gain cannot be obtained at a lower transmission rate. Also, it is shown that the gamma quantizer is realtively robust to the variation of pdf shaper and signal variance. Moreover, as the transmission rate increases, the performance of DPCM for the input signal with large variance is worse than that of DPCM for the signal with small variance due to the increase of overload noise. According to our simuladiton results, the mismatch effects of pdf shape and variance appear to yield more degradatin than that of correlation in a DPCM system.

• Smart Structures and Systems
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• v.14 no.3
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• pp.347-365
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• 2014

The main objective of this paper is to develop an innovative methodology for the vibration suppression control of the multiple degrees-of-freedom (MDOF) flexible structure. The proposed structure represented in this research as a clamped-free-free-free truss type plate is rotated by motors. The controller has two loops for tracking and vibration suppression. In addition to stabilizing the actual system, the proposed feedback control is based on a genetic algorithm (GA) to seek the primary optimal control gain for tracking and stabilization purposes. Moreover, input shaping is introduced for the control scheme that limits motion-induced elastic vibration by shaping the reference command. Experimental results are presented, demonstrating that, in the control loop, roll and yaw angles track control and elastic mode stabilization. It was also demonstrated that combining the input shaper with the proportional-integral-derivative (PID) feedback method has been shown to yield improved performance in controlling the flexible structure system. The broad range of problems discussed in this research is valuable in civil, mechanical, and aerospace engineering for flexible structures with MDOM motion.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.6-12
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• 2010

A sigma-delta modulator based class-D audio amplifier is presented. Parallel digital input is serialized to two-bit output by a fourth-order digital sigma-delta noise shaper. The output of the digital sigma-delta noise shaper is applied to a fourth-order analog sigma-delta modulator whose three-level output drives power switches. The pulse density modulated (PDM) output of the power switches is low-pass filtered by an LC-filter. The PDM output of the power switches is fed back to the input of the analog sigma-delta modulator. The first integrator of the analog sigma-delta modulator is a hybrid of continuous-time (CT) and switched-capacitor (SC) integrator. While the sampled input is applied to SC path, the continuous-time feedback signal is applied to CT path to suppress the noise of the PDM output. The class-D audio amplifier is fabricated in a standard $0.13-{\mu}m$ CMOS process and operates for the signal bandwidth from 100-Hz to 20-kHz. With 4-${\Omega}$ load, the maximum output power is 18.3-mW. The total harmonic distortion plus noise and dynamic range are 0.035-% and 80-dB, respectively. The modulator consumes 457-uW from 1.2-V power supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.8
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• pp.1283-1291
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• 2002

In this paper, the PLL driven by the DDFS is designed on the schematic using the Q-logic cell based library and is implemented using FPGA QL32 x16B. The measurement results of the frequency synthesizer switching speed were agreement with a register. The simulated results show that the clock delay was generated after eleven clock and if input is random, It has influence on output DA converter has to be very extensive. Therefore, the DDFS used noise shaper to drive PLL by regular interval for input state. Also the bandwidth of DA converter very extensive, the simulation shows that the variation of small input control word is better than the switching speed of PLL.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.35 no.11
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• pp.1423-1428
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• 2011

This paper proposes a learning input shaper with nonlinear actuator dynamics to reduce the residual vibration of flexible systems. The controller is composed of an estimator of the time constant of the nonlinear actuator dynamics, a recursive least squares method, and an iterative updating algorithm. The updating mechanism is modified by introducing a vibration measurement function to cope with the dynamics of nonlinear actuators. The controller is numerically evaluated with respect to parameter convergence and control performance by using a benchmark pendulum system. The feasibility and applicability of the controller are demonstrated by comparing its control performance to that of an existing controller algorithm.

• Proceedings of the Korean Nuclear Society Conference
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• 1995.05a
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• pp.973-979
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• 1995

The input equivalent noise charge (ENC) of hydrogenated amorphous silicon radiation detector diodes was measured and analyzed. The noise sources of amorphous silicon diodes were analyzed into three sources; shot noise, flicker noise and thermal noise from the contact resistance. By comparing the measured ENC with the calculated signal charge in uniform generation case, the signal-to-noise ratio (S/N) for the sample diodes is estimated as a function of the detector bias and the shaping time of Gaussian pulse shaper. The maximum S/N occurred at the bias level just above the full depletion voltage for shaping time of 2∼3 ${\mu}$sec. The developed method is useful in optimum design or amorphous silicon p-i-n diodes for charged particulate radiation spectroscopy.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.