• 스마트미디어저널
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• 제4권2호
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• pp.55-61
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• 2015

A bandwidth-enhanced ultra-wide band (UWB) CMOS balun-LNA is implemented as a part of a software defined radio (SDR) receiver which supports multi-band and multi-standard. The proposed balun-LNA is composed of a single-to-differential converter, a differential-to-single voltage summer with inductive shunt peaking, a negative feedback network, and a differential output buffer with composite common-drain (CD) and common-source (CS) amplifiers. By feeding the single-ended output of the voltage summer to the input of the LNA through a feedback network, a wideband balun-LNA exploiting negative feedback is implemented. By adopting a source follower-based inductive shunt peaking, the proposed balun-LNA achieves a wider gain bandwidth. Two LNA design examples are presented to demonstrate the usefulness of the proposed approach. The LNA I adopts the CS amplifier with a common gate common source (CGCS) balun load as the S-to-D converter for high gain and low noise figure (NF) and the LNA II uses the differential amplifier with the ac-grounded second input terminal as the S-to-D converter for high second-order input-referred intercept point (IIP2). The 3 dB gain bandwidth of the proposed balun-LNA (LNA I) is above 5 GHz and the NF is below 4 dB from 100 MHz to 5 GHz. An average power gain of 18 dB and an IIP3 of -8 ~ -2 dBm are obtained. In simulation, IIP2 of the LNA II is at least 5 dB higher than that of the LNA I with same power consumption.

• 한국전자파학회논문지
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• 제24권11호
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• pp.1055-1063
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• 2013

저 잡음 증폭기는 RF 수신단의 필수적인 요소이며, 다양한 무선시스템에서 사용하기 위하여 넓은 주파수 범위에서 동작하도록 요구된다. 전압 이득, 반사 손실, 잡음 지수, 선형성과 같은 중요한 성능지표들을 신중히 다루어서, 제안하는 LNA의 주요한 성능으로 역할을 하게끔 한다. Buffer 단에서 peaking 인덕터를 사용하며 전체적으로 cascade 구조로써 inductive shunt feedback을 LNA 입력 단에 성공적으로 적용하였다. 광대역 정합 주파수를 얻기 위한 설계식은 상대적으로 간단한 회로구성을 통해 도출된다. 입력 임피던스의 주파수 응답 분석을 위하여 pole과 zero를 광대역 응답을 실현하기 위한 특성으로 기술하였다. 입력 단에 게이트와 드레인 사이의 인덕터는 출력의 3차 고조파를 감소시킴으로 선형성을 크게 향상시킬 수 있다. 제안하는 회로를 $0.18{\mu}m$의 CMOS 공정으로 제작하였고, Pad를 포함한 광대역 LNA의 칩 면적은 $0.202mm^2$이다. 측정 결과는 1.5~13 GHz에서 입력손실은 -7 dB 이하이고, 전압 이득은 8 dB 이상이며, 잡음 지수는 6~9 dB 정도이다. 그리고 IIP3는 8 GHz에서 2.5 dBm이며, 1.8 V 전압에서 14 mA 전류를 소모한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.100-108
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• 2014

Low noise amplifier (LNA) is an integral component of RF receiver and frequently required to operate at wide frequency bands for various wireless system applications. For wideband operation, important performance metrics such as voltage gain, return loss, noise figure and linearity have been carefully investigated and characterized for the proposed LNA. An inductive shunt feedback configuration is successfully employed in the input stage of the proposed LNA which incorporates cascaded networks with a peaking inductor in the buffer stage. Design equations for obtaining low and high impedance-matching frequencies are easily derived, leading to a relatively simple method for circuit implementation. Careful theoretical analysis explains that input impedance can be described in the form of second-order frequency response, where poles and zeros are characterized and utilized for realizing the wideband response. Linearity is significantly improved because the inductor located between the gate and the drain decreases the third-order harmonics at the output. Fabricated in $0.18{\mu}m$ CMOS process, the chip area of this wideband LNA is $0.202mm^2$, including pads. Measurement results illustrate that the input return loss shows less than -7 dB, voltage gain greater than 8 dB, and a little high noise figure around 6-8 dB over 1.5 - 13 GHz. In addition, good linearity (IIP3) of 2.5 dBm is achieved at 8 GHz and 14 mA of current is consumed from a 1.8 V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.443-450
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• 2014

This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.