• 약학회지
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• 제45권3호
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• pp.282-286
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• 2001

To investigate the different mechanism between ATP and compound 48/80 (C$_{48}$80/)-induced histamine release, we observed effects of calcium antagonists in histamine release of rat peritoneal mast cells. Verapamil and diltiazem (voltage-dependent calcium channel blocker) and TMB-8 (a blocker of intracellular calcium release) significantly inhibited ATP-induced histamine release, but did not inhibit $C_{48}$80/-induced histamine release. Econazole (a blocker of receptor-operated calcium channel) dose-dependently inhibited both ATP and $C_{48}$80/-induced histamine release, but inhibitory effect of econazole in ATP-induced histamine release was more potent than that in $C_{48}$80/-induced histamine. EGTA dose-dependently inhibited ATP and $C_{48}$80/-induced histamine release, but $C_{48}$80/-induced histamine release was slightly inhibited by high concentrations (>2 mM) of EGTA. These results suggest that ATP-induced histamine release is related to broth intracellular calcium release and extracellular calcium influx via voltage-dependent calcium channel and receptor-operated calcium channel. $C_{48}$80/-induced histamine release is related to extracellular calcium influx, especially by receptor-operated calcium channel rather than voltage-dependent calcium channel.

• 대한전기학회논문지
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• 제37권12호
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• pp.903-913
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• 1988

본 논문의 전기철도의 AT급전방식에서 통신선에 미치는 유도장해에 관하여 컴토하엿다. 전기철도에서 통신선에 대한 유도장애는 상시 유도전압과 고장시 이상유도전압 및 잡음유도전압이 있다. 이 논문은 AT급전방식에서 통신선에 미치는 유도전압을 계산하는 앨고리즘을 도출하였으며 급전선 지락 사고시에 지락전류 계산 알고리즘을 유도하였다. 이 유도된 알고리즘을 이용하여 컴퓨터나 프로그램 팩키지화 하였다. 이 개발된 컴퓨터 프로그램 팩키지는 모의 시스템에 적용하여 그 타당성을 검증하였으며 AT급전방식에서 통신선에 대한 적절한 보호대책을 제시 및 평가할 수 있도록 하였다. 이 팩키지 프로그램은 전기철도 부설시 또는 통신선을 전기철도에 인접하여 가설시 적절한 보호대책을 평가 할 수 있으므로 아주 유용하게 이용되리라 기대된다.

• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.406-414
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• 2014

Significant penetration of induction motor loads into residential neighborhood and commercial regions of local transmission systems at least partially determine a vulnerability to a fault induced delayed voltage recovery (FIDVR) event. Highly concentrated induction motor loads with constant torque could stall in response to low voltages associated with system faults. FIDVR is caused by wide spread stalling of small HVAC units (residential air conditioner) during transmission level faults. An under voltage load shedding scheme (UVLS) can be an effective component in a strategy to manage FIDVR risk and limit the any potential disturbance. Under Voltage Load Shedding take advantage of the plan to recovery the voltage of the system by shedding the load ways to alleviation FIDVR.

• Journal of information and communication convergence engineering
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• 제5권2호
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• pp.150-154
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• 2007

Transponders of RFID system are classified as active or passive depending on the type of power supply they use. In passive transponders the data carrier has to obtain its power from the induced voltage. The induced voltage is converted into direct current using a low loss bridge rectifier and then smoothed. In practice, the induced voltage in the transponder coil is variable according to the coupling coefficient k and the load resistance ($R_L$). Therefore, the rectified voltage is unstable and the transponder of RFID is unstable sometimes. In this paper, a voltage-dependent shunt resistor ($R_s$) circuits are designed and inserted in parallel with the load resistance of RFID transponder in order to improve the stability of power.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2000년도 KIASC Conference 2000 / 2000년도 학술대회 논문집
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• pp.185-188
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• 2000

The voltage induced in the superconducting background magnet system is analyzed according to the calculation of self inductance and mutual inductance. The voltage induced by blip and compensation coils of the background magnet system is about 6.4V. In order to charge the main background magnet, the power supply must provide the minimum voltage of 1.1 kV. the compensation coils have an influence on the field distribution. The compensation coils result in the decreasing center field about 2.67%. It can remarkably decrease the ac losses and the voltage on the current leads of the background magnet.

• 한국자기학회지
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• 제26권2호
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• pp.62-66
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• 2016

포탄에 묻혀있는 탐지코일에서 유도되는 전압으로부터 총구를 떠나는 포탄의 초기속도를 계산하기 위하여 링 형태의 자석, 요크 및 탐지코일로 모델을 구성하였다. 자기장 해석에 의해 탐지코일의 유도전압에서 구한 마스터 곡선으로부터 포탄의 초기속도를 구할 수 있다. 탐지코일의 유도전압은 포탄에 묻혀있는 탐지코일 직경의 크기에 영향을 받는데, 직경의 크기가 증가하면 유도전압도 비례하여 증가한다. 탐지코일에서 유도되는 전압의 직경 효과를 감안한 초기속도 변화에 대한 정보를 입력하면 목표에서 포탄이 정확하게 폭발할 수 있다.

• 한국산학기술학회논문지
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• 제16권1호
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• pp.713-719
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• 2015

통신 회선에 대한 전력선 전자유도 전압을 측정할 때, 일반 통신 케이블의 쉬스 층 및 측정 대상 통신 회선 접지의 상호 접속 관계에 따른 전압 변화를 비교 분석하였다. 케이블 양측 쉬스 접지 저항이 평균 $42.6{\Omega}$으로 유사한 상태에서 쉬스를 분리 접지하고 유도 전압을 측정하면 쉬스 접지를 하지 않은 상태에서 측정한 유도 전압에 대하여 10 % 미만 감소된다. 어느 한 쪽을 공통으로 접지하면 약 50 % 감소되고 양측을 모두 공통으로 하면 90 % 넘게 감소된다. 이것은 국제전기통신연합(ITU)에서 제공하는 계산식으로 계산하였을 때의 결과와 유사한 것으로 분석되었다. 아울러 ITU의 계산식을 활용하여 양측 쉬스 접지 저항 값을 변화시킬 때의 유도 전압 변화를 시뮬레이션하여 비교 분석한 결과, 실제 현장에서 쉬스 접지 저항 기준이 $100{\Omega}$이고 전화 국사의 저항이 보통 $10{\Omega}$ 이하인 점을 감안할 때 측정 오차율은 약 10 % 이하가 된다.

• 전자공학회논문지A
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• 제29A권7호
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• pp.82-88
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• 1992

This paper presents one of the first comprehensive studies of how hot electron degradation impacts the input offset voltage of a CMOS differential amplifiers. This study utilizes the concept of a virtual source-coupled MOSFET pair in order to evaluate offset voltaged egradation directly from individual device measurement. Next, analytical models are developed to describe the offset voltage degradation. These models are used to examine how hot electron induced offset voltage is affected with the device parameters.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.428-431
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• 2003

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $113.4{\AA}$ and $814{\AA}$, which have the gate area 10-3cm2. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.209-212
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• 2004

In this paper, The stress induced leakage currents of thin silicon oxides is investigated in the nano scale structure implementation for Soc. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The channel current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $41\square\;and\;113.4\square,$ which have the channel width x length 10x1um, respectively. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhitory state.