• Journal of Information Technology Applications and Management
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• v.11 no.2
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• pp.29-43
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• 2004

As the development of an information technique, gradually, mobile device is going to be miniaturized and operates at high speed. By such the requirements, the devices using a flash memory as a storage media are increasing. The flash memory consumes low power, is a small size, and has a fast access time like the main memory. But the flash memory must erase for recording and the erase cycle is limited. JFFS is a representative filesystem which reflects the characteristics of the flash memory. JFFS to be consisted of LSF structure, writes new data to the flash memory in sequential, which is not related to a file size. Mounting a filesystem or an error recovery is achieved through the sequential approach. Therefore, the mounting delay time is happened according to the file system size. This paper proposes a MJFFS to use a multi-checkpoint information to manage a mass flash file system efficiently. A MJFFS, which improves JFFS, divides a flash memory into the block for suitable to the block device, and stores file information of a checkpoint structure at fixed interval. Therefore mounting and error recovery processing reduce efficiently a number of filesystem access by collecting a smaller checkpoint information than capacity of actual files. A MJFFS will be suitable to a mobile device owing to accomplish fast mounting and error recovery using advantage of log foundation filesystem and overcoming defect of JFFS.

• Journal of Korea Multimedia Society
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• v.23 no.2
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• pp.293-300
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• 2020

Since the communication networks like the Internet collapses at disaster and calamity sites, a maintenance system that can be operated offline is required for the maintenance of various facilities. In this paper, we propose a system that memory tags attached on the facilities may transmit the emergency manual to a smart-phone, and the smart phone displays it off-line. The main issue is to design low energy mode memory tags. This study presents two kinds of methods and analyzes each's energy consumption mode. The first one is to develop memory tags by using one chip, and the next one is to design memory tags by forming multi-modules. Both ways show proper application fields under the low energy mode. This research selects the off-line maintenance system by using one chip design, and proposes the direction of contents for enhancing the effectiveness of the system. And we expect that this memory tags will be valuable for disaster scenes as well as battle fields.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.10
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• pp.78-88
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• 1990

To evaluate the performance of a multiprocessor system, a discrete event model of memory interference in the system employing multiple-bus interconnection networks is proposed. An analytic model of the system is presented and then simulator models are implemented for cross-verifying the analytic results and simulation results. The simulator model takes as input the number of processors, the number of memory modules, the number of buses and the local memory miss ratio. The model produces as output the memory bandwidth, the processor, memory module and bus utilization and the bus contention ratio. Using the model in the design of the system, it is possible to evaluate the system performance by analyzing the interaction of the input parameters.

• Journal of the Korea Society of Computer and Information
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• v.24 no.8
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• pp.9-17
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• 2019

In this paper, we propose a block mapping technique applicable to NAND flash memory. In order to use the NAND flash memory with the operating system and the file system developed on the basis of the hard disk which is mainly used in the general PC field, it is necessary to use the system software known as the FTL (Flash Translation Layer). FTL overcomes the disadvantage of not being able to overwrite data by using the address mapping table and solves the additional features caused by the physical structure of NAND flash memory. In this paper, we propose a new mapping method based on the block mapping method for efficient use of the NAND flash memory. In the case of the proposed technique, the data modification operation is processed by using a blank page in the existing block without using an additional block for the data modification operation, thereby minimizing the block unit deletion operation in the merging operation. Also, the frequency of occurrence of the sequential write request and random write request Accordingly, by optimally adjusting the ratio of pages for recording data in a block and pages for recording data requested for modification, it is possible to optimize sequential writing and random writing by maximizing the utilization of pages in a block.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.125-134
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• 2004

Recently, an on-chip compressed cache system was presented to alleviate the processor-memory Performance gap by reducing on-chip cache miss rate and expanding memory bandwidth. This research Presents an extended on-chip compressed cache system which also significantly expands main memory capacity. Several techniques are attempted to expand main memory capacity, on-chip cache capacity, and memory bandwidth as well as reduce decompression time and metadata size. To evaluate the performance of our proposed system over existing systems, we use execution-driven simulation method by modifying a superscalar microprocessor simulator. Our experimental methodology has higher accuracy than previous trace-driven simulation method. The simulation results show that our proposed system reduces execution time by 4-23% compared with conventional memory system without considering the benefits obtained from main memory expansion. The expansion rates of data and code areas of main memory are 57-120% and 27-36%, respectively.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.901-909
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• 1990

With a wide spread of 32 bit personal computers, a simple structure and high performance memory system have been highly required. In this paper, a memory block is constructed by using a modified hierarchical bit line in which the DRAM bit line and the latch which works as a SRAM cell are integrated by an interface gate. And the new architecture memory DSRAM(Dynamic Static RAM) is proposed by interleaving the 16 memory block. Because the DSRAM works with 16 page, the page is miss ratio becomes small and the RAS precharge time which is incurred by page miss is shortened. So the DSRAM can implement an optimum page interleaving and it has good compatibility to the existing DRAMs. The DSRAM can be widely used in small computers as well as a high performance memory system.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.105-111
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• 2013

We have developed an analog associative memory implemented with an analog array which has linear writing and erasing characteristics. The associative memory adopts a winner-take-all strategy. The operation for reading in the memory is executed with an absolute differencing circuit and a winner-take-all (WTA) circuit suitable for a nearest-match function of a content-addressable memory. We also present a system architecture that enables highly-paralleled fast writing and quick readout as well as high integration density. A multiple memory cell configuration is also presented for achieving higher integration density, quick readout, and fast writing. The system technology presented here is ideal for a real time recognition system. We simulate the function of the mechanism by menas of Hspice with $1.2{\mu}$ double poly CMOS parameters of MOSIS fabrication process.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.3
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• pp.13-19
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• 2016

Spark, an in-memory big-data processing framework is popular to use for real-time processing workload. Spark can store all intermediate data in the cluster memory so that Spark can minimize I/O access. However, when the resident memory of workload is larger that the physical memory amount of the cluster, the total performance can drop dramatically. In this paper, we analyse the factors of bottleneck on PageRank Application that needs many memory through experiment, and cluster the Spark with Tachyon File System for using memory to solve the factor of bottleneck and then we improve the performance about 18%.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.1
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• pp.87-96
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• 2006

In this paper, we examine general digital evidence collection process which is according to RFC3227 document[l], and establish specific steps for memory information collection. Besides, we include memory dump process to existing digital evidence collection process, and examine privacy information through dumping real user's memory and collecting pagefile which is part of virtual memory system. Especially, we discovered sensitive data which is like password and userID that exist in the half of pagefiles. Moreover, we suggest each analysis technique and computer forensic process for memory information and virtual memory.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.233-236
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• 1998

In this paper, we present a novel approach named a shared library as an active memory object for application software development of large-scale real-time systems. Unlike the general passive shared memory, shared library proposed in this paper can be activated as an execution object. Moreover this is not tightly coupled with application programs unlike the normal libraries. To implement this mechanism, operating system makes the shared memory as an active object and shared library realizes the indirect call structure. This mechanism enhanced the utilization of main memory and communication performance. And this is successfully applied to the HANbit ACE ATM switching system and the TDX-10 switching system.