• Title/Summary/Keyword: in-memory

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Design of a Low Power Digital Filter Using Variable Canonic Signed Digit Coefficients (가변 CSD 계수를 이용한 저전력 디지털 필터의 설계)

  • Kim, Yeong-U;Yu, Jae-Taek;Kim, Su-Won
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.7
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    • pp.455-463
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    • 2001
  • In this Paper, an approximate processing method is proposed and tested. The proposed method uses variable CSD (VCSD) coefficients which approximate filter stopband attenuation by controlling the precision of the CSD coefficient sets. A decimation filter for Audio Codec '97 specifications has been designed having processor architecture that consists of program/data memory, arithmetic unit, energy/level decision, and sinc filter blocks, and fabricated with 0.6${\mu}{\textrm}{m}$ CMOS sea-of-gate technology. For the combined two halfband FIR filters in decimation filter, the number of addition operations were reduced to 63.5%, 35.7%, and 13.9%, compared to worst-case which is not an adaptive one. Experimental results show that the total power reduction rate of the filter is varying from 3.8 % to 9.0 % with respect to worst-case. The proposed approximate processing method using variable CSD coefficients is readily applicable to various kinds of filters and suitable, especially, for the speech and audio applications, like oversampling ADCs and DACs, filter banks, voice/audio codecs, etc.

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Inverse Characterization Method Based on 9 Channel Tone Response Curves for Display Device (디스플레이 장치를 위한 9개 채널 계조 응답 곡선에 기반한 역 특성화 기법)

  • Im, Hye-Bong;Cho, Yang-Ho;Park, Kee-Hyon;Ha, Yeong-Ho
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.42 no.5 s.305
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    • pp.85-94
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    • 2005
  • Display characterization, deriving the relationship between digital input values and the corresponding CIEXYZ tri-stimulus values, is important to reproduce the accurate color in color management system. The relationship can be estimated from the nine channel TRCs(tone response curves) and the result of this characterization method is better than that of using three channel TRCs. However, the inverse display characterization using nine channel TRCs cannot be directly inverted because the CIEXYZ values corresponding to each of RGB values are inseparable. Accordingly, inverse display characterization is usually implemented by the 3D-LUT (look-up table) method. Although the result of 3B-LUT is accurate, creating the 3D-LUT requires a lot of memory space and considerable amount of measurements. Therefore the inverse characterization method is proposed based on the modeling of channel-dependent values and nine channel inverse process based on the GOG(gain, offset gamma) model. The proposed method enhances the accuracy of display characterization and reduces the complexity and the number of measurements data required for accuracy in 3-D LUT.

A 12b 100MS/s 1V 24mW 0.13um CMOS ADC for Low-Power Mobile Applications (저전력 모바일 응용을 위한 12비트 100MS/s 1V 24mW 0.13um CMOS A/D 변환기)

  • Park, Seung-Jae;Koo, Byeong-Woo;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.8
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    • pp.56-63
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    • 2010
  • This work proposes a 12b 100MS/s 0.13um CMOS pipeline ADC for battery-powered mobile video applications such as DVB-Handheld (DVB-H), DVB-Terrestrial (DVB-T), Satellite DMB (SDMB), and Terrestrial DMB (TDMB) requiring high resolution, low power, and small size at high speed. The proposed ADC employs a three-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. A single shared and switched op-amp for two MDACs removes a memory effect and a switching time delay, resulting in a fast signal settling. A two-step reference selection scheme for the last-stage 6b FLASH ADC reduces power consumption and chip area by 50%. The prototype ADC in a 0.13um 1P7M CMOS technology demonstrates a measured DNL and INL within 0.40LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 60.0dB and a maximum SFDR of 72.4dB at 100MS/s, respectively. The ADC with an active die area of 0.92 $mm^2$ consumes 24mW at 1.0V and 100MS/s. The FOM, power/($f_s{\times}2^{ENOB}$), of 0.29pJ/conv. is the lowest of ever reported 12b 100MS/s ADCs.

The Cell Resequencing Buffer for the Cell Sequence Integrity Guarantee for the Cyclic Banyan Network (사이클릭 벤얀 망의 셀 순서 무결성 보장을 위한 셀 재배열 버퍼)

  • 박재현
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.41 no.9
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    • pp.73-80
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    • 2004
  • In this paper, we present the cell resequencing buffer to solve the cell sequence integrity problem of the Cyclic banyan network that is a high-performance fault-tolerant cell switch. By offering multiple paths between input ports and output ports, using the deflection self-routing, the Cyclic banyan switch offer high reliability, and it also solves congestion problem for the internal links of the switch. By the way, these multiple paths can be different lengths for each other. Therefore, the cells departing from an identical source port and arriving at an identical destination port can reach to the output port as the order that is different from the order arriving at input port. The proposed cell resequencing buffer is a hardware sliding window mechanism. to solve such cell sequence integrity problem. To calculate the size of sliding window that cause the prime cost of the presented device, we analyzed the distribution of the cell delay through the simulation analyses under traffic load that have a nonuniform address distribution that express tile Property of traffic of the Internet. Through these analyses, we found out that we can make a cell resequencing buffer by which the cell sequence integrity is to be secured, by using a, few of ordinary memory and control logic. The cell resequencing buffer presented in this paper can be used for other multiple paths switching networks.

Reinforcement Mining Method for Anomaly Detection and Misuse Detection using Post-processing and Training Method (이상탐지(Anomaly Detection) 및 오용탐지(Misuse Detection) 분석의 정확도 향상을 위한 개선된 데이터마이닝 방법 연구)

  • Choi Yun-Jeong;Park Seung-Soo
    • Proceedings of the Korean Information Science Society Conference
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    • 2006.06b
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    • pp.238-240
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    • 2006
  • 네트워크상에서 발생하는 다양한 형태의 대량의 데이터를 정확하고 효율적으로 분석하기 위해 설계되고 있는 마이닝 시스템들은 목표지향적으로 훈련데이터들을 어떻게 구축하여 다룰 것인지에 대한 문제보다는 대부분 얼마나 많은 데이터 마이닝 기법을 지원하고 이를 적용할 수 있는지 등의 기법에 초점을 두고 있다. 따라서, 점점 더 에이전트화, 분산화, 자동화 및 은닉화 되는 최근의 보안공격기법을 정확하게 탐지하기 위한 방법은 미흡한 실정이다. 본 연구에서는 유비쿼터스 환경 내에서 발생 가능한 문제 중 복잡하고 지능화된 침입패턴의 탐지를 위해 데이터 마이닝 기법과 결함허용방법을 이용하는 개선된 학습알고리즘과 후처리 방법에 의한 RTPID(Refinement Training and Post-processing for Intrusion Detection)시스템을 제안한다. 본 논문에서의 RTPID 시스템은 active learning과 post-processing을 이용하여, 네트워크 내에서 발생 가능한 침입형태들을 정확하고 효율적으로 다루어 분석하고 있다. 이는 기법에만 초점을 맞춘 기존의 데이터마이닝 분석을 개선하고 있으며, 특히 제안된 분석 프로세스를 진행하는 동안 능동학습방법의 장점을 수용하여 학습효과는 높이며 비용을 감소시킬 수 있는 자가학습방법(self learning)방법의 효과를 기대할 수 있다. 이는 관리자의 개입을 최소화하는 학습방법이면서 동시에 False Positive와 False Negative 의 오류를 매우 효율적으로 개선하는 방법으로 기대된다. 본 논문의 제안방법은 분석도구나 시스템에 의존하지 않기 때문에, 유사한 문제를 안고 있는 여러 분야의 네트웍 환경에 적용될 수 있다.더욱 높은성능을 가짐을 알 수 있다.의 각 노드의 전력이 위험할 때 에러 패킷을 발생하는 기법을 추가하였다. NS-2 시뮬레이터를 이용하여 실험을 한 결과, 제안한 기법이 AOMDV에 비해 경로 탐색 횟수가 최대 36.57% 까지 감소되었음을 알 수 있었다.의 작용보다 더 강력함을 시사하고 있다.TEX>로 최고값을 나타내었으며 그 후 감소하여 담금 10일에는 $1.61{\sim}2.34%$였다. 시험구간에는 KKR, SKR이 비교적 높은 값을 나타내었다. 무기질 함량은 발효기간이 경과할수록 증하였고 Ca는 $2.95{\sim}36.76$, Cu는 $0.01{\sim}0.14$, Fe는 $0.71{\sim}3.23$, K는 $110.89{\sim}517.33$, Mg는 $34.78{\sim}122.40$, Mn은 $0.56{\sim}5.98$, Na는 $0.19{\sim}14.36$, Zn은 $0.90{\sim}5.71ppm$을 나타내었으며, 시험구별로 보면 WNR, BNR구가 Na만 제외한 다른 무기성분 함량이 가장 높았다.O to reduce I/O cost by reusing data already present in the memory of other nodes. Finally, chunking and on-line compression mechanisms are included in both models. We demonstrate that we can obtain significantly high-performanc

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Password-Based Authentication Protocol for Remote Access using Public Key Cryptography (공개키 암호 기법을 이용한 패스워드 기반의 원거리 사용자 인증 프로토콜)

  • 최은정;김찬오;송주석
    • Journal of KIISE:Information Networking
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    • v.30 no.1
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    • pp.75-81
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    • 2003
  • User authentication, including confidentiality, integrity over untrusted networks, is an important part of security for systems that allow remote access. Using human-memorable Password for remote user authentication is not easy due to the low entropy of the password, which constrained by the memory of the user. This paper presents a new password authentication and key agreement protocol suitable for authenticating users and exchanging keys over an insecure channel. The new protocol resists the dictionary attack and offers perfect forward secrecy, which means that revealing the password to an attacher does not help him obtain the session keys of past sessions against future compromises. Additionally user passwords are stored in a form that is not plaintext-equivalent to the password itself, so an attacker who captures the password database cannot use it directly to compromise security and gain immediate access to the server. It does not have to resort to a PKI or trusted third party such as a key server or arbitrator So no keys and certificates stored on the users computer. Further desirable properties are to minimize setup time by keeping the number of flows and the computation time. This is very useful in application which secure password authentication is required such as home banking through web, SSL, SET, IPSEC, telnet, ftp, and user mobile situation.

Design and Verification of PCI 2.2 Target Controller to support Prefetch Request (프리페치 요구를 지원하는 PCI 2.2 타겟 컨트롤러 설계 및 검증)

  • Hyun Eugin;Seong Kwang-Su
    • The KIPS Transactions:PartA
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    • v.12A no.6 s.96
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    • pp.523-530
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    • 2005
  • When a PCI 2.2 bus master requests data using Memory Read command, a target device may hold PCI bus without data to be transferred for long time because a target device needs time to prepare data infernally. Because the usage efficiency of the PCI bus and the data transfer efficiency are decreased due to this situation, the PCI specification recommends to use the Delayed Transaction mechanism to improve the system performance. But the mechanism cann't fully improve performance because a target device doesn't know the exact size of prefetched data. In the previous work, we propose a new method called Prefetch Request when a bus master intends to read data from the target device. In this paper, we design PCI 2.2 controller and local device that support the proposed method. The designed PCI 2.2 controller has simple local interface and it is used to convert the PCI protocol into the local protocol. So the typical users, who don't know the PCI protocol, can easily design the PCI target device using the proposed PCI controller. We propose the basic behavioral verification, hardware design verification, and random test verification to verify the designed hardware. We also build the test bench and define assembler instructions. And we propose random testing environment, which consist of reference model, random generator ,and compare engine, to efficiently verify corner case. This verification environment is excellent to find error which is not detected by general test vector. Also, the simulation under the proposed test environment shows that the proposed method has the higher data transfer efficiency than the Delayed Transaction about $9\%$.

Broadcast Content Recommender System based on User's Viewing History (사용자 소비이력기반 방송 콘텐츠 추천 시스템)

  • Oh, Soo-Young;Oh, Yeon-Hee;Han, Sung-Hee;Kim, Hee-Jung
    • Journal of Broadcast Engineering
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    • v.17 no.1
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    • pp.129-139
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    • 2012
  • This paper introduces a recommender system that is to recommend broadcast content. Our recommender system uses user's viewing history for personalized recommendations. Broadcast contents has unique characteristics as compared with books, musics and movies. There are two types of broadcast content, a series program and an episode program. The series program is comprised of several programs that deal with the same topic or story. Meanwhile, the episode program covers a variety of topics. Each program of those has different topic in general. Therefore, our recommender system recommends TV programs to users according to the type of broadcast content. The recommendations in this system are based on user's viewing history that is used to calculate content similarity between contents. Content similarity is calculated by exploiting collaborative filtering algorithm. Our recommender system uses java sparse array structure and performs memory-based processing. And then the results of processing are stored as an index structure. Our recommender system provides recommendation items through OPEN APIs that utilize the HTTP Protocol. Finally, this paper introduces the implementation of our recommender system and our web demo.

Data Cache System based on the Selective Bank Algorithm for Embedded System (내장형 시스템을 위한 선택적 뱅크 알고리즘을 이용한 데이터 캐쉬 시스템)

  • Jung, Bo-Sung;Lee, Jung-Hoon
    • The KIPS Transactions:PartA
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    • v.16A no.2
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    • pp.69-78
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    • 2009
  • One of the most effective way to improve cache performance is to exploit both temporal and spatial locality given by any program executive characteristics. In this paper we present a high performance and low power cache structure with a bank selection mechanism that enhances exploitation of spatial and temporal locality. The proposed cache system consists of two parts, i.e., a main direct-mapped cache with a small block size and a fully associative buffer with a large block size as a multiple of the small block size. Especially, the main direct-mapped cache is constructed as two banks for low power consumption and stores a small block which is selected from fully associative buffer by the proposed bank selection algorithm. By using the bank selection algorithm and three state bits, We selectively extend the lifetime of those small blocks with high temporal locality by storing them in the main direct-mapped caches. This approach effectively reduces conflict misses and cache pollution at the same time. According to the simulation results, the average miss ratio, compared with the Victim and STAS caches with the same size, is improved by about 23% and 32% for Mibench applications respectively. The average memory access time is reduced by about 14% and 18% compared with the he victim and STAS caches respectively. It is also shown that energy consumption of the proposed cache is around 10% lower than other cache systems that we examine.

Measurement of Width and Step-Height of Photolithographic Product Patterns by Using Digital Holography (디지털 홀로그래피를 이용한 포토리소그래피 공정 제품 패터닝의 폭과 단차 측정)

  • Shin, Ju Yeop;Kang, Sung Hoon;Ma, Hye Joon;Kwon, Ik Hwan;Yang, Seung Pil;Jung, Hyun Chul;Hong, Chung Ki;Kim, Kyeong Suk
    • Journal of the Korean Society for Nondestructive Testing
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    • v.36 no.1
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    • pp.18-26
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    • 2016
  • The semiconductor industry is one of the key industries of Korea, which has continued growing at a steady annual growth rate. Important technology for the semiconductor industry is high integration of devices. This is to increase the memory capacity for unit area, of which key is photolithography. The photolithography refers to a technique for printing the shadow of light lit on the mask surface on to wafer, which is the most important process in a semiconductor manufacturing process. In this study, the width and step-height of wafers patterned through this process were measured to ensure uniformity. The widths and inter-plate heights of the specimens patterned using photolithography were measured using transmissive digital holography. A transmissive digital holographic interferometer was configured, and nine arbitrary points were set on the specimens as measured points. The measurement of each point was compared with the measurements performed using a commercial device called scanning electron microscope (SEM) and Alpha Step. Transmission digital holography requires a short measurement time, which is an advantage compared to other techniques. Furthermore, it uses magnification lenses, allowing the flexibility of changing between high and low magnifications. The test results confirmed that transmissive digital holography is a useful technique for measuring patterns printed using photolithography.