• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.719-722
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• 1998

Fault simulation for large and complex sequential circuits is highly cpu-intensive task in the intergrated circuit design process. In this paper, we propose CM-SIM, a concurrent fault simulator which employs an optimal memory management strategy and simple list operations. CM-SIM removes inefficiencies and uses new dynamic memory management strategies, using contiguous array memory. Consequently, we got improved performance and reduced memory usage in concurrent fault simulation.

• Journal of information and communication convergence engineering
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• v.7 no.2
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• pp.199-202
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• 2009

Adaptive memory management is a serious issue in data stream management. Data stream differ from the traditional stored relational model in several aspect such as the stream arrives online, high volume in size, skewed data distributions. Data skew is a common property of massive data streams. We propose the predicted allocation strategy, which uses predictive processing to cope with time varying data skew. This processing includes memory usage estimation and indexing with timestamp. Our experimental study shows that the predictive strategy reduces both required memory space and latency time for skewed data over varying time.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.9
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• pp.703-711
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• 1991

In this paper, an efficient storage reclamation algorithm for RISC parallel processing in the object orented programming environments is presented. The memory management for the dynamic memory allocation and the frequent memory access in object oriented programming is the main factor that decreases RISC parallel processing performance. The proposed algorithm can be efficiently allocated the memory space of RISCy computer which is required the frequent memory access, so it can be increased RISC parallel processing performance. The proposed algorithm is verified the efficiency by implementing C language on SUN SPARC(4.3 BSD UNIX).

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.473-482
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• 2017

Hand gesture recognition is regarded as new Human Computer Interaction (HCI) technologies for the next generation of mobile devices. Previous hand gesture implementation requires a large memory and computation power for hand segmentation, which fails to give real-time interaction with mobile devices to users. Therefore, in this paper, we presents a low latency and memory-efficient hand segmentation architecture for natural hand gesture recognition. To obtain both high memory-efficiency and low latency, we propose a streaming hand contour tracing unit and a fast contour filling unit. As a result, it achieves 7.14 ms latency with only 34.8 KB on-chip memory, which are 1.65 times less latency and 1.68 times less on-chip memory, respectively, compare to the best-in-class.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 1998.10b
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• pp.7-7
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• 1998

Research activities of Russian Medical Engineering Center and Institute of Medical Materials of Shape Memory Alloys and Implants are presented as follows: ${\bullet}$ The direction of elaboration of porous shape memory alloys for medicine. ${\bullet}$ Medical and technical requirements and physical and mechanical criteria of porous shape memory implants elaboration. ${\bullet}$ Basic laws of heat-, stress- and strain-induced changes of mechanical properties, shape memory effect and superelasticity in porous TiNi-based alloys. ${\bullet}$ Methods of regulation of shape memory effect parameters in porous alloys and methods for controlling the regulation-induced changes of physical and mechanical properties. ${\bullet}$ Original technologies of elaboration of porous alloys In various fields of medicine. ${\bullet}$ Arrangement of serial production of shape memory porous implants and examples of their medical use.

• Journal of IKEEE
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• v.11 no.4
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• pp.193-197
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• 2007

We use a saturation function with memory instead of a pure saturation function to generate a limit cycle in order to find one point information of a plant in the frequency domain. The saturation function with memory is useful in the presence of noise and/or a short duration of short duration of external disturbances. We analyze the error caused by the approximation that the saturation function with memory treated as a pure saturation function. We propose a new tuning formula for PID controller which can be applied a saturation function having memory with an arbitrary memory size. We show that the proposed method is more accurate than that of the approximation method via an example.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.286-291
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• 2015

For highly scalable NAND flash memory applications, a compact ($4F^2/cell$) nonvolatile memory architecture is proposed and investigated via three-dimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.108-114
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• 2004

In this paper we propose the boot system using CF memory card and study the system implementation method. The system that is proposed in this paper basically consist of high performance microprocessor, small amount of program memory and CF memory card. And added LCD module and touch panel for the user interface. This system use the CF memory card and DRAM instead of the Flash memory, so it can reduce the system cost. And system performance is increased because of the system program running in the DRAM.

• Proceedings of the Acoustical Society of Korea Conference
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• 1994.06a
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• pp.830-835
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• 1994

In this paper, a new method of statistically evaluating an output response probability distribution of a memory type non-linear system is practically derived based on a zero-memory type non-linear equivalent system. That is, first, the objective system is approximately and functionally separated into two functional parts, i.e., a zero-memory type non-linear part and a memory type linear part according to the well-known Wiener's idea. A whole mathematical frame of the output probability distribution is evaluated in an approximate but generalized form, based on the equivalent zero-memory type non-linear part. The memory effects between the input and the output of the system are reflected in the statistical parameters and the expansion coefficients.

• Journal of Environmental Science International
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• v.27 no.11
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• pp.1023-1028
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• 2018

Shape memory materials are widely used in high-tech industries. Although shape memory polymers have been developed, they have a disadvantage, only unidirectional resilience. Shape memory polymers with bi-directional recovery resilience have been actively studied. In this study, a bidirectional shape memory polyurethane was synthesized using poly(${\varepsilon}$-caprolactone) diol, methylene dicyclohexyl diisocyanate, and hydroxyethyl acrylate. The first physical curing occurred between hard segments and hydrogen bondings when the solution was dried. The second curing in acrylate groups was performed by UV exposure. A degree of curing was analyzed by infrared spectroscopy. The shape memory properties of 2 step-cured polyurethanes were investigated as a function of UV curing time.