• 한국정보처리학회논문지
• /
• 제4권11호
• /
• pp.2832-2839
• /
• 1997

본 연구에서는 Asynchronous Transfer Mode (ATM) 계층의 기능중 유휴 가상 채널에 프로토콜 프로토콜 적합성 시험 제어 기능을 갖게 하여 Test Coordination Procedures (TCP) 채널로 활용하는 방안을 제시하였다. 프로토콜 적합성 시험을 위하여 국제 기구에서 권고하고 있는 방법중 원격 시험 방법을 선택하면 System Under Test (SUT)측에 서 능동적으로 Test Event를 발생시켜야 하는 경우에 개발자가 직접 수동적으로 운용을 하거나, Implementation Under Test (IUT)에 대한 제어 및 관찰이 불가능한 경우도 발생하게 된다. ATM망에서 프로토콜 적합성 시험시 시험 영역(Test Coverage)을 최대화하고, 오류검출 영역(Fauit Coverase)을 극대화하기 위해서는 원격시험방법보다는 분산시험방법이 적절하며, 분산시험방법을 채택할 경우 TCP를 구현하기 위하여 시험정보를 전달하기 위한 채널을 확보하는 것이 요구된다. 본 고에서 제안하고 있는 방법은 오류 검출 영역을 극대화 시키고 오퍼레이터의 개입없이 시험의 자동화 구현이 용이하고, ATM장치의 정상동작에는 영향을 주지 않음은 물론 시험제어를 위한 별도의 채널을 확보하지 않고서도 분산시험방법을 적용할 수 있다는 점 을 특징으로 들 수 있다．

• 한국정보처리학회논문지
• /
• 제6권11호
• /
• pp.3086-3096
• /
• 1999

To declare conformance of multi-protocol Implementation Under Test(IUT), every layer of the multi-protocol IUT should be tested. According to ISO9646, single-layer test method is applied to testing the highest layer of multi-protocol IUT and single-layer embedded test method is used for the layers by layer all the protocols in a multi-protocol IUT. This paper proposes a new method for testing a multi-protocol IUT. The proposed test method assumes that a multi-protocol IUT is under test and that the interfaces between the layers cannot be controlled or observed by the tester. We apply the proposed test method to TCP/IP and compare the application results with those of the existing test turns out that the proposed test method significantly reduces the number of test cases as well as the number of test events while providing the same test coverage. In addition, the proposed test method shows the capability to locate the layer that is source of failure in testing multi-protocol IUTs.

• 한국통신학회논문지
• /
• 제24권12A호
• /
• pp.2008-2014
• /
• 1999

IDDQ 테스팅은 CMOS 회로에서 발생되는 여러 종류의 물리적 결함을 효율적으로 검출하는 테스팅 방식이다. 본 논문에서는 테스트 대상회로의 게이트내부에서 발생하는 단락을 고려하여, 이 결함을 검출하기 위한 테스트 패턴을 찾아 주는 IDDQ 테스트 패턴 발생기를 구현하였다. 테스트 패턴을 생성하기 위해 게이트 종류별로 모든 내부 단락을 검출하는 게이트 테스트 벡터를 찾아냈다. 그리고 10,000개의 무작위패턴을 테스트대상 회로에 인가하여 각 게이트에서 요구되는 테스트 벡터를 발생시켜 주면 유용한 테스트 패턴으로 저장한다. 입력된 패턴들이 모든 게이트 테스트 벡터를 발생시켜 주거나 10,000개의 패턴을 모두 인가했을 경우 테스트 패턴 발생 절차를 종료한다. ISCAS '85 벤처마크 회로에 대한 실험을 통하여 기존의 다른 방식보다 성능이 우수함을 보여주었다.

• Structural Engineering and Mechanics
• /
• 제38권2호
• /
• pp.141-156
• /
• 2011

A cable stayed bridge under construction has low structural damping and is not as stable as the completed bridge. Control countermeasures, such as the installation of energy dissipating devices, are thus required. In this study, the general procedure and key issues on adopting an active control device, the active mass damper (AMD), for vibration control of cable stayed bridges under construction were studied. Taking a typical cable stayed bridge as the prototype structure; a lab-scale test structure was designed and fabricated firstly. A baseline FEM model was then setup and updated according to the modal parameters measured from vibration test on the structure. A numerical study to simulate the bridge-AMD control system was conducted and an efficient LQG-based controller was designed. Based on that, an experimental implementation of AMD control of the transverse vibration of the bridge model was performed. The results from numerical simulation and experimental study verified that the AMD-based active control was feasible and efficient for reducing dynamic responses of a complex structural system. Moreover, the discussion made in this study clarified some critical problems which should be addressed for the practical implementation of AMD control on real cable-stayed bridges.

• 한국정보과학회논문지:정보통신
• /
• 제28권3호
• /
• pp.377-388
• /
• 2001

하나의 시험 스위티를 가지고 다중 계층 프로토콜 시험대상(Implementation Under Test: IUT)을 시험하는 방안이 제안되었다[1] 기존 방법과 비교하여 이방법은 상위 프로토콜에 적용하는 단일 계층 시험 방법과 하위 프로토콜에 적용하는 내포 시험 방법을 조합하여 적용함으로써 다중 계층 프로토콜 시험 대상을 시험한다. 그러나 논문[1]은 접근 방법만 제시하였을뿐 어떻게 시험 경우를 자동으로 도출할 것인지에 대해서는 고려하지 않고 있다. 본 논문은 논문[1]에 기초하여 다중 계층 프로토콜 시험 경우 자동 생성알고리즘을 제안한다. 이를 위해 시험대상 프로토콜을 두 개의 FSM으로 정의하고 두 FSM에 대하여 pre-execution 과 carried-by 로 구성되는 트랜지션의 수행 관계를 정의한다. 제안한 알고리즘을 구현하여 간략화한 TCP/IP와 B-ISDN Signaling/Service Specific Connection Oriented Protocol (SSCOP)에 적용한다. 본논문의 다중 계층 프로토콜 시험방법은 프로토콜 사이의 인터페이스가 개방되지 않은 경우에도 시험이 가능하며 기존 시험방법에 비해서 적은 시험 경우로 동이한 커버리지를 갖는다

• 항공우주시스템공학회지
• /
• 제1권4호
• /
• pp.13-21
• /
• 2007

As one of YHF digital data link technologies, VDL Mode 2 is designed to be an air-to-ground subnetwork of the Aeronautical Telecommunication Network (ATN) based on the Open System Interconnection (OSI) architecture. VDL Mode 2 can be used in ATS Applications especially for CPDLC and ADS. And it is also expected to replace ACARS (Aircraft Communications Addressing and Reporting System) which has broadly been used in AOC for over 20 years. This paper presents the design result of VDL Mode 2 system under AOA (ACARS Over AVLC) environment for the implementation of bit-oriented ATS applications. The system is composed of airborne and ground subsystem. Airborne subsystem consists of VDR, CMU and an aircraft test equipment with CPDLC/ADS client applications for operational test and ground system consists of Ground Station which includes ground VDR and ground communication controller, simple DSP (Datalink Service Processor) and a ground test equipment with CPDLC/ADS server applications.

• 한국지진공학회:학술대회논문집
• /
• 한국지진공학회 2003년도 추계 학술발표회논문집
• /
• pp.263-270
• /
• 2003

Before the implementation of the 1992 seismic design provisions in Korea, longitudinal steels of RC bridge piers were practically lap-spliced in the plastic hinge region. Experimental investigation was made to evaluate the seismic performance of RC bridge pier specimens in a flexure/shear mode. Six circular test specimens in an aspect ratio of 2.5 (600mm in diameter) were made with test parameters confinement ratio, lap splices, and retrofit FRP materials. They were damaged under a series of artificial earthquakes with 0.22g PGA, being compatible in Korean peninsula, through the pseudo-dynamic test. Probable damages were assessed by the Park and Ang damage index. Approximate 0.1 and 0.3 damage indices were obtained for RC specimens without lap splice and with lap splice, respectively. Directly after the pseudo-dynamic test, damaged test columns were laterally actuated under inelastic reversal cyclic loadings simultaneously under a constant axial load. Through curvature measurements, residual seismic performance was evaluated for test specimens. Test results show that RC pier specimens with lap-spliced appeared to fail at low ductility, but significant improvement was obtained for the ductility of these specimens if externally wrapped with FRP.

• 품질경영학회지
• /
• 제27권4호
• /
• pp.256-265
• /
• 1999

In this paper, we Present the implementation of statistical process control software by using XLISP-STAT which is a kind of object oriented language under Windows environment. This software can be used to generate the graphic objects for various control charts, histogram and plots using the full-down menu system. This software can also be used to calculate control limits, process capability indices and test procedures for normality.

• 한국경영과학회:학술대회논문집
• /
• 대한산업공학회/한국경영과학회 1990년도 춘계공동학술대회논문집; 한국과학기술원; 28 Apr. 1990
• /
• pp.81-90
• /
• 1990

The major objective of this paper is to analyze the relationships between End-User Computing(EUC) attributes and its implementation. Reviewing the related literatures, we categorized EUC attributes into threefactors - relative advantage, compatibility, complexity. With such attributes this paper proposed a hypothetical model which explains the effect of the EUC attributes on its implementation. Under the assumption that EUC attributes affect its implementation differently according to the several contingent factors, the model included such factors as organizational size, organizational support level on the EUC activities and individual characteristics - computer experience, education level, age. Data were collected form 177 end-users of 40 Korean business firms. Hypotheses were tested using Pearson Correlation, t-test, ANOVA and the results are discussed below.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1998년도 추계종합학술대회 논문집
• /
• pp.1069-1072
• /
• 1998

Recently the development of design and automation technology and manufacturing method, has reduced the cost of chip, but it becomes more difficult to test IC chip because test technique doesn't keep up with these techniques. In case of IC testing, obtaining test vectors to be able to detect good chip or bad one is very important, but according to increasing complexity, it is very complex and difficult. Another problem is that during testing, there could be capability of physical and electrical damage on chip. Also there is difficulty in synchronization between CUT (circuit under test) and Test equipment〔1〕. Because of these difficulties, built in self test has been proposed. Not only obtaining test vectors but also reducing test time becomes hot issues nowadays. This paper presents a new test BIST(built in self test) method. Proposed BIST implementation reduces test time and obtains high fault coverage. By searching internal nodes in which are inserted test_point_cells〔2〕and allocating TPG(test pattern generation) stages, test length becomes much shorter.