• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2832-2839
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• 1997

In this paper, a testing architecture and procedure that an idle ATM virtual channel can be utilized for TCP channel is proposed. Four kinds or methodologies for protocol conformance testing have been standardized in ISO. Remote testing method used popularly have some disadvantages that developer must operate system manually in case of System Under Test (SUT) active testing and we cannot control and observe Implementation Under Test (IUT) often. It is proper to adopt distribute testing method than remote test in order to maximize test coverage and optimize fault coverage for conformance testing in ATM systems, and it is required that TCP channel is prepared for distribute testing method. The proposed architecture can adopt distributed testing method without extra physical channel for testing control. Also we can maximize the test coverage and implement the automation of testing without intervention of operator sustaining normal operation of ATM equipment.

• The Transactions of the Korea Information Processing Society
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• v.6 no.11
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• pp.3086-3096
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• 1999

To declare conformance of multi-protocol Implementation Under Test(IUT), every layer of the multi-protocol IUT should be tested. According to ISO9646, single-layer test method is applied to testing the highest layer of multi-protocol IUT and single-layer embedded test method is used for the layers by layer all the protocols in a multi-protocol IUT. This paper proposes a new method for testing a multi-protocol IUT. The proposed test method assumes that a multi-protocol IUT is under test and that the interfaces between the layers cannot be controlled or observed by the tester. We apply the proposed test method to TCP/IP and compare the application results with those of the existing test turns out that the proposed test method significantly reduces the number of test cases as well as the number of test events while providing the same test coverage. In addition, the proposed test method shows the capability to locate the layer that is source of failure in testing multi-protocol IUTs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.2008-2014
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• 1999

IDDQ testing is an effective testing method to detect various physical defects occurred in CMOS circuits. In this paper, we consider intra-gate shorts within circuit under test and implement IDDQ test pattern generator to find test patterns which detect considered defects. In order to generate test patterns, gate test vectors which detect all intra-gate shorts have to be found by type of gates. Random test sets of 10,000 patterns are applied to circuit under test. If an applied pattern generates a required test vector of any gate, the pattern is saved as an available test pattern. When applied patterns generate all test vectors of all gats or 10,000 patterns are applied to circuit under test, procedure of test pattern generation is terminated. Experimental results for ISCAS'85 bench mark circuits show that its efficiency is more enhanced than that obtained by previously proposed methods.

• Structural Engineering and Mechanics
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• v.38 no.2
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• pp.141-156
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• 2011

A cable stayed bridge under construction has low structural damping and is not as stable as the completed bridge. Control countermeasures, such as the installation of energy dissipating devices, are thus required. In this study, the general procedure and key issues on adopting an active control device, the active mass damper (AMD), for vibration control of cable stayed bridges under construction were studied. Taking a typical cable stayed bridge as the prototype structure; a lab-scale test structure was designed and fabricated firstly. A baseline FEM model was then setup and updated according to the modal parameters measured from vibration test on the structure. A numerical study to simulate the bridge-AMD control system was conducted and an efficient LQG-based controller was designed. Based on that, an experimental implementation of AMD control of the transverse vibration of the bridge model was performed. The results from numerical simulation and experimental study verified that the AMD-based active control was feasible and efficient for reducing dynamic responses of a complex structural system. Moreover, the discussion made in this study clarified some critical problems which should be addressed for the practical implementation of AMD control on real cable-stayed bridges.

• Journal of KIISE:Information Networking
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• v.28 no.3
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• pp.377-388
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• 2001

An approach for testing multi-protocol Implementation Under Test (IUT) with a single test suite has been proposed in[1]. this paper proposes an algorithm called Multi-protocol Test Method (MPTM) for automatic test case generation based on that approach. With the MPTM, a multi-protocol IUT consisting of two protocol layers is modeled as two Finite State Machines (FSMs), and the relationships between the transitions of the two FSMs are defined as a set of transition relationships pre-execution and carried-by. The proposed algorithm is implemented and applied to a simplified TCP/IP and B-ISDN Signaling/SSCOP. MPTM is able to test the multi-protocol IUT even though the interfaces between the protocol layers are not exposed. It results in that the proposed MPTM allows the same test coverage as conventional test methods even with fewer numbers of test cases.

• Journal of Aerospace System Engineering
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• v.1 no.4
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• pp.13-21
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• 2007

As one of YHF digital data link technologies, VDL Mode 2 is designed to be an air-to-ground subnetwork of the Aeronautical Telecommunication Network (ATN) based on the Open System Interconnection (OSI) architecture. VDL Mode 2 can be used in ATS Applications especially for CPDLC and ADS. And it is also expected to replace ACARS (Aircraft Communications Addressing and Reporting System) which has broadly been used in AOC for over 20 years. This paper presents the design result of VDL Mode 2 system under AOA (ACARS Over AVLC) environment for the implementation of bit-oriented ATS applications. The system is composed of airborne and ground subsystem. Airborne subsystem consists of VDR, CMU and an aircraft test equipment with CPDLC/ADS client applications for operational test and ground system consists of Ground Station which includes ground VDR and ground communication controller, simple DSP (Datalink Service Processor) and a ground test equipment with CPDLC/ADS server applications.

• Proceedings of the Earthquake Engineering Society of Korea Conference
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• 2003.09a
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• pp.263-270
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• 2003

Before the implementation of the 1992 seismic design provisions in Korea, longitudinal steels of RC bridge piers were practically lap-spliced in the plastic hinge region. Experimental investigation was made to evaluate the seismic performance of RC bridge pier specimens in a flexure/shear mode. Six circular test specimens in an aspect ratio of 2.5 (600mm in diameter) were made with test parameters confinement ratio, lap splices, and retrofit FRP materials. They were damaged under a series of artificial earthquakes with 0.22g PGA, being compatible in Korean peninsula, through the pseudo-dynamic test. Probable damages were assessed by the Park and Ang damage index. Approximate 0.1 and 0.3 damage indices were obtained for RC specimens without lap splice and with lap splice, respectively. Directly after the pseudo-dynamic test, damaged test columns were laterally actuated under inelastic reversal cyclic loadings simultaneously under a constant axial load. Through curvature measurements, residual seismic performance was evaluated for test specimens. Test results show that RC pier specimens with lap-spliced appeared to fail at low ductility, but significant improvement was obtained for the ductility of these specimens if externally wrapped with FRP.

• Journal of Korean Society for Quality Management
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• v.27 no.4
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• pp.256-265
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• 1999

In this paper, we Present the implementation of statistical process control software by using XLISP-STAT which is a kind of object oriented language under Windows environment. This software can be used to generate the graphic objects for various control charts, histogram and plots using the full-down menu system. This software can also be used to calculate control limits, process capability indices and test procedures for normality.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1990.04a
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• pp.81-90
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• 1990

The major objective of this paper is to analyze the relationships between End-User Computing(EUC) attributes and its implementation. Reviewing the related literatures, we categorized EUC attributes into threefactors - relative advantage, compatibility, complexity. With such attributes this paper proposed a hypothetical model which explains the effect of the EUC attributes on its implementation. Under the assumption that EUC attributes affect its implementation differently according to the several contingent factors, the model included such factors as organizational size, organizational support level on the EUC activities and individual characteristics - computer experience, education level, age. Data were collected form 177 end-users of 40 Korean business firms. Hypotheses were tested using Pearson Correlation, t-test, ANOVA and the results are discussed below.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1069-1072
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• 1998

Recently the development of design and automation technology and manufacturing method, has reduced the cost of chip, but it becomes more difficult to test IC chip because test technique doesn't keep up with these techniques. In case of IC testing, obtaining test vectors to be able to detect good chip or bad one is very important, but according to increasing complexity, it is very complex and difficult. Another problem is that during testing, there could be capability of physical and electrical damage on chip. Also there is difficulty in synchronization between CUT (circuit under test) and Test equipment〔1〕. Because of these difficulties, built in self test has been proposed. Not only obtaining test vectors but also reducing test time becomes hot issues nowadays. This paper presents a new test BIST(built in self test) method. Proposed BIST implementation reduces test time and obtains high fault coverage. By searching internal nodes in which are inserted test_point_cells〔2〕and allocating TPG(test pattern generation) stages, test length becomes much shorter.