• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 2004.07a
• /
• pp.109-109
• /
• 2004

• Journal of Electrical Engineering and Technology
• /
• v.6 no.6
• /
• pp.842-848
• /
• 2011

The current study proposes the design of a hybrid series-parallel resonant converter (SPRC) and a three-stage Cockcroft-Walton voltage multiplier for precisely adjusting the power generated by a continuous wave (CW) $CO_2$ laser. The design of a hybrid SPRC, called LCC resonant converter, is described, and the fundamental approximation of a high-voltage and high-frequency (HVHF) transformer with a resonant tank is discussed. The results of the current study show that the voltage drop and ripple of a three-stage Cockcroft-Walton voltage multiplier depend on frequency. The power generated by a CW $CO_2$ laser can be precisely adjusted by a variable-frequency controller using a DSP (TMS320F2812) microprocessor. The proposed LCC converter could be used to obtain a maximum laser output power of 23 W. Moreover, it could precisely adjust the laser output power within 4.3 to 23 W at an operating frequency range of 187.5 to 370 kHz. The maximum efficiency of the $CO_2$ laser system is approximately 16.5%, and the minimum ripple of output voltage is about 1.62%.

• Journal of Advanced Navigation Technology
• /
• v.14 no.1
• /
• pp.66-73
• /
• 2010

This paper proposes the frequency multiplier using diplexer based on CRLH transmission line with dualband characteristic. The diplexer is separated the output signals of harmonic generator, which is generated the harmonic signals using nonlinear device. The diplexer consists of the inphase power divider, 0o/90o phase controller and dual-band quadrature hybrid coupler. This send out the selecting output signals of the harmonic signals and suppresses out of signals. To validate a function of multiplier, the harmonic generator and diplexer with 2 GHz and 3 GHz operating frequency range is implemented. As a result, the proposed frequency multiplier is operated normally.

• Proceedings of the IEEK Conference
• /
• 2002.07b
• /
• pp.852-855
• /
• 2002

This paper presents a design of FIR near-equiripple Nyquist filters having zero-intersymbol interference (ISI) and low sensitivity to timing jitter, with coefficients taking only discrete values. Using an affine scaling linear programming algorithm, an optimum discrete coefficient set can be obtained in a feasible computational time. Also presented is a pipelined multiplier-free FIR filter realization with periodically time-varying (PTV) coefficients based on a hybrid form suitable for Nyquist filter. The realization exploits the coefficient symmetry to reduce the hardware by about one half. High speed computation and low power consumption are achieved by its pipelined and low fan-out structure.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.497-500
• /
• 2005

This paper presents a design of a hybrid sensor chip which integrates an A/D converter module and a phase measurement module for measuring power line phase. Recursive sliding DFT based phase measurement module is designed using time shared multiplier which can reduce the size of SoC implementation. A/D converter is based on the sigma delta modulation in order to minimize the implementation space of the analog part and designed to obtain 8-bit resolution. Computer simulations and FPGA implementation are performed to verify hybrid sensor chip design. The hybrid sensor chip for 4-channel power line phase measurement is fabricated by using 0.35 micrometer CMOS process.

• Journal of IKEEE
• /
• v.7 no.1 s.12
• /
• pp.9-15
• /
• 2003

An optimized finite-field multiplier is proposed for encryption and error correction devices. It is based on a modified Linear Feedback Shift Register (LFSR) which has lower power consumption and smaller area than prior LFSR-based finite-field multipliers. The proposed finite field multiplier for GF(2n) multiplies two n-bit polynomials using polynomial basis to produce $z(x)=a(x)^*b(x)$ mod p(x), where p(x) is a irreducible polynomial for the Galois Field. The LFSR based on a serial multiplication structure has less complex circuits than array structures and hybrid structures. It is efficient to use the LFSR structure for systems with limited area and power consumption. The prior finite-field multipliers need 3${\cdot}$m flip-flops for multiplication of m-bit polynomials. Consequently, they need 6${\cdot}$m latches because one flip-flop consists of two latches. The proposed finite-field multiplier requires only 4${\cdot}$m latches for m-bit multiplication, which results in 1/3 smaller area than the prior finite-field multipliers. As a result, it can be used effectively in encryption and error correction devices with low-power consumption and small area.

• Proceedings of the Korean Information Science Society Conference
• /
• 2003.04a
• /
• pp.275-277
• /
• 2003

본 논문에서는 GF(2$^{m}$ )상에서 비트 직렬 Linear Feedback Shift Register (LFSR) 구조와 비트 병렬 셀룰라 오토마타(Cellular Automata, CA)구조를 혼합한 새로운 하이브리드(Hybrid) 형식의 A$B^2$곱셈기를 제안한다. 본 논문에서 제안한 곱셈기는 제곱연산을 위해 구조적으로 가장 간단한 비트 직렬 구조를 이용하고, 곱셈연산을 위해 시간 지연이 적은 비트 병렬 구조를 이용한다. 제안된 구조는 LFSR의 구조적인 특징과 Periodic Boundary CA (PBCA)의 특성, 그리고 All One Polynomial (AOP)의 특성을 조화시킴으로써 기존의 구조에 비하여 정규성을 높이고 지연 시간을 줄일 수 있는 구조이다. 제안된 곱셈기는 공개키 암호화의 핵심이 되는 지수기의 구현을 위한 효율적인 기본구조로 사용될 것으로 기대된다.

• Nuclear Engineering and Technology
• /
• v.55 no.10
• /
• pp.3844-3853
• /
• 2023

Although radiation and chemotherapy methods for cancer therapy have advanced significantly, surgical resection is still recommended for most cancers. Therefore, intraoperative imaging studies have emerged as a surgical tool for identifying tumor margins. Intraoperative imaging has been examined using conventional imaging devices, such as optical near-infrared probes, gamma probes, and ultrasound devices. However, each modality has its limitations, such as depth penetration and spatial resolution. To overcome these limitations, hybrid imaging modalities and tracer studies are being developed. In a previous study, a multi-modal laparoscope with silicon photo-multiplier (SiPM)-based gamma detection acquired a 1 s interval gamma image. However, improvements in the near-infrared fluorophore (NIRF) signal intensity and gamma image central defects are needed to further evaluate the usefulness of multi-modal systems. In this study, an attempt was made to change the NIRF image acquisition method and the SiPM-based gamma detector to improve the source detection ability and reduce the image acquisition time. The performance of the multi-modal system using a complementary metal oxide semiconductor and modified SiPM gamma detector was evaluated in a phantom test. In future studies, a multi-modal system will be further optimized for pilot preclinical studies.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.9
• /
• pp.1-9
• /
• 2007

For an efficient implementation of cryptosystems based on arithmetic in a finite field $GF(2^n)$, their hardware implementation is an important research topic. To construct a multiplier with low area complexity, the divide-and-conquer technique such as the original Karatsuba-Ofman method and multi-segment Karatsuba methods is a useful method. Leone proposed an efficient parallel multiplier with low area complexity, and Ernst at al. proposed a multiplier of a multi-segment Karatsuba method. In [1], the authors proposed new $MSK_5$ and $MSK_7$ methods with low area complexity to improve Ernst's method. In [3], the authors proposed a method which combines $MSK_2$ and $MSK_3$. In this paper we propose an efficient multiplication method by combining $MSK_2,\;MSK_3\;and\;MSK_5$ together. The proposed method reduces $116{\cdot}3^l$ gates and $2T_X$ time delay compared with Gather's method at the degree $25{\cdot}2^l-2^l with l>0.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.4
• /
• pp.94-104
• /
• 2008

In this paper, we propose a new architecture of multiplier-and-accumulator (MAC) for high speed multiplication and accumulation arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator which has the largest delay in MAC was removed and its function was included into CSA, the overall performance becomes to be elevated. The proposed CSA tree uses 1's complement-based radix-2 modified booth algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of operands. The CSA propagates the carries by the least significant bits of the partial products and generates the least significant bits in advance for decreasing the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits not the output of the final adder for improving the performance by optimizing the efficiency of pipeline scheme. The proposed architecture was synthesized with $250{\mu}m,\;180{\mu}m,\;130{\mu}m$ and 90nm standard CMOS library after designing it. We analyzed the results such as hardware resource, delay, and pipeline which are based on the theoretical and experimental estimation. We used Sakurai's alpha power low for the delay modeling. The proposed MAC has the superior properties to the standard design in many ways and its performance is twice as much than the previous research in the similar clock frequency.