• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.9
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• pp.1747-1754
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• 2016

This paper presents a high accuracy and fast hybrid on-chip temperature sensor. The proposed temperature sensor combines a SAR type temperature sensor with a ${\Sigma}{\Delta}$ type temperature sensor. The SAR type temperature sensor has fast temperature searching time but it has more error than the ${\Sigma}{\Delta}$ type temperature sensor. The ${\Sigma}{\Delta}$ type temperature sensor is accurate but it is slower than the SAR type temperature sensor. The proposed temperature sensor uses both the SAR and ${\Sigma}{\Delta}$ type temperature sensors, so that the proposed temperature sensor has high accuracy and fast temperature searching. Also, the proposed temperature sensor includes a temperature error compensating circuit by storing the temperature errors in a memory circuit after chip fabrication. The proposed temperature sensor was fabricated in 3.3V CMOS $0.35{\mu}m$ process. Its temperature resolution, power consumption, and area are $0.15^{\circ}C$, $540{\mu}W$, and $1.2mm^2$, respectively.

• Journal of Life Science
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• v.19 no.8
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• pp.1055-1061
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• 2009

${\alpha}$-amino-3-hydroxy-5-methyl-4-isoxazole propionate (AMPA) receptors are widespread throughout the central nervous system and appear to serve as synaptic receptors for fast excitatory synaptic transmission mediated by glutamate. Their modulation is believed to affect learning and memory. To identify the interaction proteins for the AMPA receptor subunit glutamate receptor-interacting protein 1 (GRIPl), GRIP1 interactions with armadillo family protein p0071/plakophilin-4 were investigated. GRIP1 protein bound to the tail region of p0071/plakophilin-4 but not to other armadillo family protein members in a yeast two-hybrid assay. The "S-X-V" motif at the carboxyl (C)-terminal end of p0071/plakophilin-4 is essential for interaction with GRIP1. p0071/plakophilin-4 interacted with the Postsynaptic density-95/Discs large/Zona occludens-1 (PDZ) domains of GRIPI in the yeast two-hybrid assay, as is indicated also by Glutathione S-transferase (GST) pull-down, and co-immunoprecipitated with GRIP1 antibody in brain fraction. The findings of this study provide evidence that p0071/plakophilin-4 is an interactor of GRIP1.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.183-184
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• 2013

Two main MBE growth techniques have been used: plasma-assisted MBE (PA-MBE), which utilizes a rf plasma to supply active nitrogen, and ammonia MBE, in which nitrogen is supplied by pyrolysis of NH3 on the sample surface during growth. PA-MBE is typically performed under metal-rich growth conditions, which results in the formation of gallium droplets on the sample surface and a narrow range of conditions for optimal growth. In contrast, high-quality GaN films can be grown by ammonia MBE under an excess nitrogen flux, which in principle should result in improved device uniformity due to the elimination of droplets and wider range of stable growth conditions. A drawback of ammonia MBE, on the other hand, is a serious memory effect of NH3 condensed on the cryo-panels and the vicinity of heaters, which ruins the control of critical growth stages, i.e. the native oxide desorption and the surface reconstruction, and the accurate control of V/III ratio, especially in the initial stage of seed layer growth. In this paper, we demonstrate that the reliable and reproducible growth of GaN on Si (110) substrates is successfully achieved by combining two MBE growth technologies using rf plasma and ammonia and setting a proper growth protocol. Samples were grown in a MBE system equipped with both a nitrogen rf plasma source (SVT) and an ammonia source. The ammonia gas purity was ＞99.9999% and further purified by using a getter filter. The custom-made injector designed to focus the ammonia flux onto the substrate was used for the gas delivery, while aluminum and gallium were provided via conventional effusion cells. The growth sequence to minimize the residual ammonia and subsequent memory effects is the following: (1) Native oxides are desorbed at $750^{\circ}C$ (Fig. (a) for [$1^-10$] and [001] azimuth) (2) 40 nm thick AlN is first grown using nitrogen rf plasma source at $900^{\circ}C$ nder the optimized condition to maintain the layer by layer growth of AlN buffer layer and slightly Al-rich condition. (Fig. (b)) (3) After switching to ammonia source, GaN growth is initiated with different V/III ratio and temperature conditions. A streaky RHEED pattern with an appearance of a weak ($2{\times}2$) reconstruction characteristic of Ga-polarity is observed all along the growth of subsequent GaN layer under optimized conditions. (Fig. (c)) The structural properties as well as dislocation densities as a function of growth conditions have been investigated using symmetrical and asymmetrical x-ray rocking curves. The electrical characteristics as a function of buffer and GaN layer growth conditions as well as the growth sequence will be also discussed. Figure: (a) RHEED pattern after oxide desorption (b) after 40 nm thick AlN growth using nitrogen rf plasma source and (c) after 600 nm thick GaN growth using ammonia source for (upper) [110] and (lower) [001] azimuth.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.401-404
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• 2015

This paper proposes a high-performance in-loop filter in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. HEVC uses in-loop filter consisting of deblocking filter and SAO(Sample Adaptive Offset) to solve the problems of quantization error which causes image degradation. In the proposed in-loop filter encoder hardware architecture, the deblocking filter and SAO has a 2-level hybrid pipeline structure based on the $32{\times}32CTU$ to reduce the execution time. The deblocking filter is performed by 6-stage pipeline structure, and it supports minimization of memory access and simplification of reference memory structure using proposed efficient filtering order. Also The SAO is implemented by 2-statge pipeline for pixel classification and applying SAO parameters and it uses two three-layered parallel buffers to simplify pixel processing and reduce operation cycle. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 205K logic gates in TSMC 0.13um process. At 110MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 30fps in realtime.

• The KIPS Transactions:PartD
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• v.12D no.5 s.101
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• pp.689-698
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• 2005

Various systems are used to provide the location based services. But, the existing systems have some problems which have difficulties in dealing with faster services for above million people. In order to solve it, a multi-level DBMS which supports both fast data processing and large data management support should be used. The multi-level DBMS with snapshots has all the data existing in disk database and the data which are required to be processed for fast processing are managed in main memory database as snapshots. To optimize performance of this system for location based services, the query classification component which classifies the queries for efficient snapshot usage is needed. In this paper, the query classification component in multi-level DBMS for location based services is designed and implemented. The proposed component classifies queries into three types: (1) memory query, (2) disk query, (3) hybrid query, and increases the rate of snapshot usage. In addition, it applies division mechanisms which divide aspatial and spatial filter condition for partial snapshot usage. Hence, the proposed component enhances system performance by maximizing the usage of snapshot as a result of the efficient query classification.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.33-40
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• 2005

This paper describes a design of FFT/IFFT Core(FFT256/2k), which is an essential block in terrestrial DMB modem. It has four operation modes including 256/512/1024/2048-point FFT/IFFT in order to support the Eureka-147 transmission modes. The hybrid architecture, which is composed of R2SDF and R2SDC structure, reduces memory by $62\%$ compared to R2SDC structure, and the SQNR performance is improved by TS_CBFP(Two Step Convergent Block Floating Point). Timing simulation results show that it can operate up to 50MHz(a)2.5-V, resulting that a 2048-point FFT/IFFT can be computed in 41-us. The FFT256/2k core designed in Verilog-HDL has about 68,400 gates and 58,130 RAM. The average power consumption estimated using switching activity is about 113-mW, and the total average SQNR of over 50-dB is achieved. The functionality of the core was fully verified by FPGA implementation.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.691-698
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• 2006

TCP/IP Offload Engine (TOE) is a technology that processes TCP/IP on a network adapter instead of a host CPU to reduce protocol processing overhead from the host CPU. There have been some approaches to implementing TOE: software TOE based on an embedded processor; hardware TOE based on ASIC implementation; and hybrid TOE in which software and hardware functions are combined. In this paper, we designed software modules and hardware modules for a hybrid TOE on an FPGA that had two processor cores. Software modules are based on the embedded Linux. Hardware modules are for data transmission (TX) and reception (RX). One core controls the TX path and the other controls the RX path of the Linux. This TX/RX path separation mechanism can reduce task switching overheads between processes and overcome poor performance of single embedded processor. Hardware modules deal with creating headers for outgoing packets, processing headers of incoming packets, and fetching or storing data from or to the host memory by DMA. These can make it possible to improve the performance of data transmission and reception. We proved performance of the TOE with separated transmission and reception paths by performing experiments with a TOE network adapter that was equipped with the FPGA having processor cores.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.4
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• pp.189-198
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• 2015

Most IoT-related approaches have tried to establish the relation by connecting the network between things. The proposed research will present how the pervasive interaction of eco-system formed by touching the objects between humans and things can be recognized on purpose. By collecting and sharing the detected patterns among all kinds of things, we can construct the environment which enables individualized interactions of different objects. To perform the aforementioned, we are going to utilize technical procedures such as event-driven signal processing, pattern matching for signal recognition, and hardware in the loop simulation. We will also aim to implement the prototype of sensor processor based on Arduino MCU, which can be integrated with system using Arduino-Matlab/Simulink hybrid-interoperation environment. In the experiment, we use piezo transducer to detect the vibration or vibrates the surface using acoustic wave, which has specific frequency spectrum and individualized signal shape in terms of time axis. The signal distortion in time and frequency domain is recorded into memory tracer within sensor processor to extract the meaningful pattern by comparing the stored with lookup table(LUT). In this paper, we will contribute the initial prototypes for the acoustic touch processor by using off-the-shelf MCU and the integrated framework based on Matlab/Simulink model to provide the individualization of the touch-sensing for the user on purpose.

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1719-1726
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• 1996

In the OR-parallel execution of logic programs, binding environments have a critical impact on the performance. Particularly, this is true for distributed execution on parallel systems with a non-single address space. The reason is that in such systems, the remote accesses across processing elements deteriorate the performance. To solve this problem, some binding methods were previously proposed specifically for a non-single address space. However, compared with the binding methods for a single address space, they are far less efficient due to the overhead of newly introduced operations such as environment closing and back-unification, In this paper, we propose a new binding environment is a hybrid that combines both the binding methods for a single address space and those for anon-single address space. It acomplishes high efficiency by making closing operations unnecessary both at unification and at back-unification, while mainthing the restricted accesses.

• The KIPS Transactions:PartA
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• v.14A no.7
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• pp.421-434
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• 2007

Among many other CG generated natural scenes, the representation of ocean surfaces is one of the most complicated and time-consuming problem because of its large extent and complex surface movement. We present a hybrid method to represent and animate unbound deep-water ocean surfaces by utilizing graphics processor as both simulation and rendering core. Our technique is mainly based on spectral approaches that generate a high-detailed height field using Fourier transform on a 2D regular grid. Additionally, we incorporate Gerstner model and generate low-detailed height field on a 2D projected grid in order to represent large waves and main structure of ocean surface. There is no interruption between CPU and GPU, and no need to transfer simulation results from the system memory to graphics hardware because the entire simulation and rending processes are done on graphics processor. As a result we can synthesize and render realistic water surfaces in real-time. Proposed techniques are readily adoptable to real-time applications such as computer games that have heavy work load on CPU but still demand plausible natural scenes.