• Journal of Advanced Marine Engineering and Technology
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• v.11 no.2
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• pp.37-50
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• 1987

In an effort to conserve electric power, variable voltage variable frequency pulse width modulated (PWM) inverters are being applied increasingly to the variable speed control of the induction motors. The use of the PWM technique in motor drive applications is considered advantageous in many ways. For industrial applications, the PWM drive obtains its DC input through simple uncontrolled rectification of the commercial AC line and is favored for its good power factor, good efficiency, its relative freedom regulation problem, and mainly for its ability to operate the motor with nearly sinusoidal current waveforms. The purpose of this paper is to design a three phase natural sampled PWM inverter using microprocessor with simple control algorithm and hybrid control circuit has been built to implement this PWM scheme. In this system, the microprocessor can be used only for calculations directly related to motor control tasks by the design of hybrid circuit which sends PWM signals to the motor.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2003.05a
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• pp.362-367
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• 2003

A new mechanical-electrical hybrid passive dam ping treatment is proposed to improve the performance of structural vibration control. The proposed hybrid passive damping system consists of a constrained layer damping treatment and a shunt circuit. In a passive mechanical constrained layer damping, a viscoelastic material damping layer is used to control the structural vibration modes in high frequency range. The passive electrical damping is designed for targeting the vibration amplitude in the low frequency range. The governing equations of motion are derived through the Hamilton's principle. The obtained mathematical model is validated experimentally. The presented theoretical and experimental techniques provide invaluable tools for controlling the multiple modes of a vibrating structure over a wide frequency band.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.3
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• pp.16-23
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• 1998

In this paper, we present a fast and efficient Iterative Improvement Partitioning(IIP) technique for VLSI circuits and hybrid bucket structures on its implementation. The IIP algorithms are very widely used in VLSI circuit partition due to their time efficiency. As the performance of these algorithms depends on choices of moving cell, various methods have been proposed. Specially, Cluster-Removal algorithm by S. Dutt significantly improved partition quality. We indicate the weakness of previous algorithms wjere they used a uniform method for choice of cells during for choice of cells during the improvement. To solve the problem, we propose a new IIP technique that selects the method for choice of cells according to the improvement status and present hybrid bucket structures for easy implementation. The time complexity of proposed algorithm is the same with FM method and the experimental results on ACM/SIGDA benchmark circuits show improvment up to 33-44%, 45%-50% and 10-12% in cutsize over FM, LA-3 and CLIP respectively. Also with less CUP tiem, it outperforms Paraboli and MELO represented constructive-partition methods by about 12% and 24%, respectively.

• Journal of the Optical Society of Korea
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• v.18 no.5
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• pp.564-568
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• 2014

We present a 25-Gb/s optical transmitter composed of a Si ring modulator and CMOS driver circuit. The Si ring modulator is realized with 220-nm Si-on-insulator process and the driver circuit with 65-nm CMOS process. The modulator and the driver are hybrid-integrated on the printed circuit board with bonding wires. The driver is designed so that the parasitic bonding wire inductance provides enhanced driver bandwidth. The transmitter successfully demonstrates 25-Gb/s operation.

• Journal of Korea Society of Industrial Information Systems
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• v.6 no.2
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• pp.74-79
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• 2001

The Stewing Motor has applied for engineering technology and that special used to auto mobile technology, robot technology and still more automatic machinery. If it make used to the motor for automatic machinery. That have high precision step of motor and high efficiency. n order to operation in this paper, the static position of motor to have analyzing, comparison of constant voltage control methode and constant current methode. And designed to a controller circuit of 4 phase unipolar driving and 2 phase bipolar driving of stepping motor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.85-92
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• 2009

This paper proposes a full-search block-matching motion estimation circuit with hybrid architecture combining systolic arrays and adder trees for an MPEG-4 encoder. The proposed circuit uses systolic arrays for motion estimation with a small number of clock cycles and adder trees to reduce required circuit resources. The interpolation circuit for 1/2 pixel motion estimation consists of six adders, four subtracters and ten registers. We improved the circuit performance by resource sharing and efficient scheduling techniques. We described the motion estimation circuit for integer and 1/2 pixels at RTL in Verilog HDL. The logic-level circuit synthesized by using 130nm standard cell library contains 218,257 gates and can process 94 D1($720{\times}480$) image frames per second.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.25-32
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• 2011

Networks-on-chip (NoC) is emerging as a key technology to overcome severe bus traffics in ever-increasing complexity of the Multiprocessor systems-on-chip (MPSoC); however traditional electrical interconnection based NoC architecture would be faced with technical limits of bandwidth and power consumptions in the near future. In order to cope with these problems, a hybrid optical NoC architecture which use both electrical interconnects and optical interconnects together, has been widely investigated. In the hybrid optical NoCs, wormhole switching and simple deterministic X-Y routing are used for the electrical interconnections which is responsible for the setup of routing path and optical router to transmit optical data through optical interconnects. Optical NoC uses circuit switching method to send payload data by preset paths and routers. However, conventional hybrid optical NoC has a drawback that concurrent transmissions are not allowed. Therefore, performance improvement is limited. In this paper, we propose a new routing algorithm that uses circuit switching and adaptive algorithm for the electrical interconnections to transmit data using multiple paths simultaneously. We also propose an efficient method to prevent livelock problems. Experimental results show up to 60% throughput improvement compared to a hybrid optical NoC and 65% power reduction compared to an electrical NoC.

• Journal of Power Electronics
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• v.15 no.3
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• pp.652-659
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• 2015

This paper presents a new hybrid soft switching dc-dc converter with a low circulating current and high circuit efficiency. The proposed hybrid converter includes two sub-converters sharing two power switches. One is a three-level PWM converter and the other is a LLC converter. The LLC converter and the three-level converter share the lagging-leg switches and extend the zero-voltage switching (ZVS) range of the lagging-leg switches from nearly zero to full load since the LLC converter can be operated at f_sw (switching frequency) $\approx$ f_r (series resonant frequency). A passive snubber is used on the secondary side of the three-level converter to decrease the circulating current on the primary side, especially at high input voltage and full load conditions. Thus, the conduction losses due to the circulating current are reduced. The output sides of the two converters are connected in series. Energy can be transferred from the input voltage to the output load within the whole switching period. Finally, the effectiveness of the proposed converter is verified by experiments with a 1.44kW prototype circuit.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.11
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• pp.17-22
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• 2000

A novel and robust direct parameter extraction method for hybrid-p equivalent circuit model of HBT is proposed. A new expression that can accurately resolve the base internal resistance from the measured S-parameters is derived, and it is not sensitive to the values of parasitic access inductance values. Based on the expression, six analytical expressions for the other parameters is developed and these expressions for hybrid-p equivalent circuit modeling ensure robust, fast, and reliable parameter extraction.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.650-652
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• 2001

The permanent magnet in hybrid step motor is magnetized to the axial direction. Accordingly the 2D analysis method such as 2D finite element method cannot guarantee the analysis accuracy. In this paper, the characteristics of hybrid type step motor are analyzed by using 3D equivalent magnetic circuit network method(3D EMCNM). 3D EMCNM supplements magnetic equivalent circuit by numerical technique using distributive magnetic circuit parameter and 3D EMCNM is used for the accurate and efficient analysis. The validity of the analysis results is confirmed by comparing with the experimental ones.