• Communications of the Korean Mathematical Society
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• v.30 no.2
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• pp.109-121
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• 2015

In this paper, we investigate horizontal lightlike hypersurfaces of Robertson-Walker spacetimes. Some results involving the unique existence of the screen distribution and the symmetry of the induced Ricci curvature tensor of horizontal lightlike hypersurfaces are presented. We also obtain some properties concerning the symmetry and the parallelism of the second fundamental forms of such lightlike hypersurfaces.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.792-795
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• 2005

The guide-ways of precision machine tools are one of important element of machine tools. It has usually a pair of surfaces for constraint of one direction with bearing. In the case of precision machine tools, non-contact bearing such as hydrostatic bearing and aerostatic bearing is adopted usually. In this case, profiles of rails has effect on straightness and the clearance of bearing has effect on stiffness of guide way, which changes to higher if clearance changes to smaller. The clearance is varied along moving table according to relative distance of pair of rails. The relative distance of pair of rail can be divided by three properties. First and second properties are straightness of each pair of rail and bearing pad. And, third is parallelism about pair of rails and pairs of bearing pad. There are several methods for measuring straightness of each surface such as reversal method, sequential two point method, and way straightness. These straightness measuring methods are always acquiring deviation of profile from eliminating linear fitted inclined line and don't have the information of parallelism. Therefore, to get the small clearance for high stiffness, the straightness of rail and bearing pad and parallelism about pair of rails and pair of bearing pads are measured for correction such as regrinding, reassembling and lapping. In this research, new and easy method for measuring parallelism of pair of rails is suggested. Two displacement probe and sensor stage, which is carry on the displacement sensor, are needed. The simulation and experiment was accomplished about pair of horizontal guide way to confirm the measurement of parallelism. And, the third probe is added to measure the straightness of each rails by sequential two point method. From the estimation of combined these two methods, it is confirmed that the profiles of a pairs of rails can be measured.

• Journal of the Chungcheong Mathematical Society
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• v.25 no.4
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• pp.731-738
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• 2012

Let L(M) be the bundle of all linear frames over $M,\;u$ an arbitrarily given point of L(M), and ${\nabla}\;:\;\mathfrak{X}(M)\;{\times}\;\mathfrak{X}(M)\;\rightarrow\;\mathfrak{X}(M)$ a linear connection on L(M). Then the following results are well known: the horizontal subspace and the connection form at the point $u$ may be written in terms of local coordinates of $u\;{\epsilon}\;L(M)$ and Christoffel's symbols defined by $\nabla$. These results are very fundamental on the study of the theory of connections. In this paper we show that the local expressions of those at the point $u$ do not depend on the choice of a local coordinate system around the point $u\;{\epsilon}\;L(M)$, which is rarely seen. Moreover we give full explanations for the following fact: the covariant derivative on M which is defined by the parallelism on L(M), determined from the connection form above, coincides with $\nabla$.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.3
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• pp.13-18
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• 1984

This paper suggests an algorithm which can perform microoperations (MO'S) in parauel by considering concurrency of MO'S and resource allocation in horizontal microprogams. The algorithm can be obtained the result which reduces execution time and the space of control memory in microprogrammed digital systems by minimizing the total number of microinctructions by combining MO'5, which can be performed in paiallel by assigning a weight to each MO in the SLM (straight line microprogram), into a microinstruction.

• Journal of Biomedical Engineering Research
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• v.6 no.2
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• pp.13-14
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• 1985

We have developed a microprogramir!able signal processor for real-time ultrasonic signal processing. Processing speed was increased by the parallelism in horizontal microprogram using 104bits microcode and the Pipelined architecture. Control unit of the signal processor was designed by microprogrammed architec- ture and writable control store (WCS) which was interfaced with host computer, APPLE- ll . This enables the processor to develop and simulate various digital signal processing algorithms. The performance of the processor was evaluated by the Fast Fourier Transform (FFT) program. The execution time to perform 16 bit 1024 points complex FF7, radix-2 DIT algorithm, was about 175 msec with IMHz master Clock. We can use this processor to Bevelop more efficient signal processing algorithms on the biological signal processing.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1449-1453
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• 1987

A microprogrammable Bit Slice Sinal Processor for image processing is implemented. Processing speed is increased by the parallelism in horizontal microprogram using 120bits microcode, pipelined architecture, 2 bank memory switching that interfaces with the Host through DMA, a variable clock control, overflow checking H/W,look-up table method and cache memory. With this processor, a DCT algorithm which uses 2-D FFT is performed. The execution time for $512{\times}512{\times}8$ image is 12 sec when 16 bit operation is runned, and the recovered image has acceptable quality with MSE 0.276%.

• Journal of Biomedical Engineering Research
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• v.6 no.2
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• pp.15-22
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• 1985

We have developed a microprogramir!able signal processor for real-time ultrasonic signal processing. Processing speed was increased by the parallelism in horizontal microprogram using 104bits microcode and the Pipelined architecture. Control unit of the signal processor was designed by microprogrammed architec- ture and writable control store (WCS) which was interfaced with host computer, APPLE- ll . This enables the processor to develop and simulate various digital signal processing algorithms. The performance of the processor was evaluated by the Fast Fourier Transform (FFT) program. The execution time to perform 16 bit 1024 points complex FF7, radix-2 DIT algorithm, was about 175 msec with IMHz master Clock. We can use this processor to Bevelop more efficient signal processing algorithms on the biological signal processing.

• Journal of the korean academy of Pediatric Dentistry
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• v.28 no.1
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• pp.185-194
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• 2001

This study was designed to evaluate the effects of angulation changes of head posture on the enlargement ratios of a lateral headfilm depending on the vortical or horizontal rotation of the objects. A device was constructed to measure regional changes of enlargement ratios. The device was held within the cephalostat and cephalograms recorded at each measured degrees of the device tilting, vertically and horizontally. The enlargement ratios of the horizontal, vertical, and angular measurements on the films taken at each tilted angulations were obtained and compared with those on the films taken without rotation. In summary, the enlargement ratios of the horizontal linear measurements were decreased during horizontal rotations. The enlargement ratios of vortical measurements of the right side on the film were increased and those of the left side were decreased by the horizontal rotations. Enlargement ratios of horizontal measurements were affected further than those of vertical measurements by the same angular changes of the horizontal rotations. Therefore, a disruption of parallelism between the object's midsagittal plane and the film could result in distortion of the image while vertical rotation around the object's porionic axis would not significantly affect the enlargement ratios on the headfilm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.4
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• pp.699-706
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• 2008

H.264/AVC is a new international standard for the compression of video images, in which a deblocking filter has been adopted to remoye blocking artifacts. This paper proposes an efficient architecture of deblocking filter in H.264/AVC. By making good use of data dependence between neighboring $4{\times}4$ blocks, the memory sire is reduced and the throughput of the deblocking filter processing is increased. The designed deblocking filter further enhances the parallelism by simultaneously executing horizontal and vertical filtering within a macroblock in pipeline method and adopting overlap between macroblocks. The implementation result shows that the proposed architecture enhances the performance of deblocking filter processing from 1.75 to 4.23 times than that of the conventional deblocking filter. Hence the Proposed architecture of deblocking filter is able to perform real-time deblocking in high-resolution($2048{\times}1024$) video applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.102-116
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• 2009

There have been lots of researches for H.264/AVC performance enhancement on a multi-core processor. The enhancement has been performed through parallelization methods. Parallelization methods can be classified into a task-level parallelization method and a data level parallelization method. A task-level parallelization method for H.264/AVC decoder is implemented by dividing H.264/AVC decoder algorithms into pipeline stages. However, it is not suitable for complex and large bitstreams due to poor load-balancing. Considering load-balancing and performance scalability, we propose a horizontal data level parallelization method for H.264/AVC decoder in such a way that threads are assigned to macroblock lines. We develop a mathematical performance expectation model for the proposed parallelization methods. For evaluation of the mathematical performance expectation, we measured the performance with JM 13.2 reference software on ARM11 MPCore Evaluation Board. The cycle-accurate measurement with SoCDesigner Co-verification Environment showed that expected performance and performance scalability of the proposed parallelization method was accurate in relatively high level