• The Journal of the Korea institute of electronic communication sciences
• /
• v.18 no.3
• /
• pp.433-440
• /
• 2023

When the reflector is hit by a vehicle or returned by a storm, an event is generated by the impact sensor and a trigger is operated. The trigger processing algorithm of this paper compares the X, Y, and Z values of the gyro sensor with the registered values and proposes to drive them to the original values by the operation of the 3-axis driving motor. And by recognizing the vehicle license plate, if the vehicle is stolen or a social problem, information is provided to the police operation network. When the reflector is stolen or moved, it has a registered GPS value, so it operates the theft monitoring function to process it.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.18 no.5
• /
• pp.1238-1259
• /
• 2024

Previous studies on joint optimization of computation offloading and service caching policies in Mobile Edge Computing (MEC) have often neglected the impact of dependency-aware subtasks, edge server resource constraints, and multiple users on policy formulation. To remedy this deficiency, this paper proposes a many-objective joint optimization dependency-aware task offloading and service caching model (MaJDTOSC). MaJDTOSC considers the impact of dependencies between subtasks on the joint optimization problem of task offloading and service caching in multi-user, resource-constrained MEC scenarios, and takes the task completion time, energy consumption, subtask hit rate, load variability, and storage resource utilization as optimization objectives. Meanwhile, in order to better solve MaJDTOSC, a many-objective evolutionary algorithm TSMSNSGAIII based on a three-stage mating selection strategy is proposed. Simulation results show that TSMSNSGAIII exhibits an excellent and stable performance in solving MaJDTOSC with different number of users setting and can converge faster. Therefore, it is believed that TSMSNSGAIII can provide appropriate sub-task offloading and service caching strategies in multi-user and resource-constrained MEC scenarios, which can greatly improve the system offloading efficiency and enhance the user experience.

• Journal of Internet Technology
• /
• v.19 no.6
• /
• pp.1691-1698
• /
• 2018

In this paper, we are to address the problem of item recommendations to users in shopping malls selling several different kinds of items, e.g., daily necessities such as cosmetics, detergent, and food ingredients. Most of current recommendation algorithms are developed for sites selling only one kind of items, e.g., music or movies. To devise efficient recommendation algorithms suitable for repetitively purchasing items, we give a method to implicitly assign ratings for these items by making use of repetitive purchase counts, and then use these ratings for the purpose of recommendation prediction with the help of user-based collaborative filtering and item-based collaborative filtering algorithms. We also propose associate item-based recommendation algorithm. Items are called associate items if they are frequently bought by users at the same time. If a user is to buy some item, it is reasonable to recommend some of its associate items. We implement user-based (item-based) collaborative filtering algorithm and associate item-based algorithm, and compare these three algorithms in view of the recommendation hit ratio, prediction performance, and recommendation coverage, along with computation time.

• Journal of the Korea Society of Computer and Information
• /
• v.10 no.2 s.34
• /
• pp.69-78
• /
• 2005

As the study and use of P2P systems are diversified, the effect of excessive amount of traffic, which occurs in searching peers' resource and is considered as a network bandwidth Problem, cannot let the matter Pass without making a protest. In case P2P application doesn't reduce network traffic, it can be much effected to use bandwidth smoothly in the internet environment where various network applications lie scattered and there will be inconvenience when many network users makes use of related applications . In this Paper, we propose a pure P2P model based-broadcasting technique for producing successful hit ratio and traffic amount in the weakly connected environment based-P2P system where situation of peers' connection and exit is ambiguous . The proposed searching technique is designed/implemented to improve a resident problem in the related system and we have estimated the performance of the proposed searching technique comparing our technique with the existing broadcasting based-searching technique .

• Design & Manufacturing
• /
• v.12 no.1
• /
• pp.41-46
• /
• 2018

This study proves the causes of cylinder and piston jam by scratches which is the fatal problem of hydraulic breaker through the thermal analysis and thermal-structural coupled field analysis. The trouble from the scratch is a complex problem which can be caused by manufacturing process (this is an internal factor) and the users mistake or contamination in the hydraulic circuit (these are an external factor). Hence, it's not easy to investigate the causes, also hard to prevent the recurrence. In this reason, hydraulic breaker manufacturers are trying to improve the manufacturing process such as machining, heat treatment, grinding, cleaning, also to prevent the contamination in hydraulic circuit and to remove the remains. It's being managed thoroughly by manufacturers. This study shows the effect of the temperature rise by the frictional heat generated when the piston hits the tool on the hydraulic oil while the hydraulic breaker is operating, also the temperature distribution when it starts to affect main components of hydraulic breaker. The stress and the amount of deformation also could be found through thermal-structural coupled field analysis. It proved that the stress and deformation are proportionally increased according to the temperature rise in hit area, and it affects the cylinder and the viscosity of hydraulic oil inside the cylinder when it heats up beyond the certain temperature.

• Journal of Communications and Networks
• /
• v.12 no.1
• /
• pp.52-66
• /
• 2010

Since large objects consume substantial resources, web proxy caching incurs a fundamental trade-off between performance (i.e., hit-ratio and latency) and overhead (i.e., resource usage), in terms of caching and relaying large objects to users. This paper investigates how and to what extent the current dedicated-server based web proxy caching scheme is affected by large file transfers in a high bandwidth campus network environment. We use a series of trace-based performance analyses and profiling of various resource components in our experimental squid proxy cache server. Large file transfers often overwhelm our cache server. This causes a bottleneck in a web network, by saturating the network bandwidth of the cache server. Due to the requests for large objects, response times required for delivery of concurrently requested small objects increase, by a factor as high as a few million, in the worst cases. We argue that this cache bandwidth bottleneck problem is due to the fundamental limitations of the current centralized web proxy caching model that scales poorly when there are a limited amount of dedicated resources. This is a serious threat to the viability of the current web proxy caching model, particularly in a high bandwidth access network, since it leads to sporadic disconnections of the downstream access network from the global web network. We propose a peer-to-peer cooperative web caching scheme to address the cache bandwidth bottleneck problem. We show that it performs the task of caching and delivery of large objects in an efficient and cost-effective manner, without generating significant overheads for participating peers.

• The KIPS Transactions:PartA
• /
• v.10A no.2
• /
• pp.83-92
• /
• 2003

RAID 5 is a widely-used technique used to construct disk systems of high reliability and performance. This paper proposes APGOC (Adaptive Parity Group On Cache) organization on cache to solve "small write" problem of RAID 5 especially in OLTP (On-Line Transaction Processing System) environments. In our approach, when user process makes a request for a file to kernel, the information on the read/write characteristics is added to the file data structure of the file system. With this information, data and parity cache can be managed interchangeably through parity fetching. Therefore we can enhance the cache utilization and improve the disk request response time. Our method is analyzed and evaluated with a simulation method. Comparing with previous works, we observed about 6~l3% of performance enhancement.hancement.

• Journal of Internet Computing and Services
• /
• v.16 no.5
• /
• pp.19-27
• /
• 2015

Due to the advantages of fast read/write operation and low power consumption, SSD(Solid State Drive) is now widely adopted as storage device of smart phone, laptop computer, server, etc. However, the shortcomings of SSD such as limited number of write operations and asymmetric read/write operation lead to the problem of shortened life span of SSD. Therefore, the block replacement policy of SSD used as cache for HDD is very important. The existing solutions for improving the lifespan of SSD including the LARC scheme typically employ the LRU algorithm to manage the SSD blocks, which may increase the miss rate in SSD due to the replacement of frequently used block instead of rarely used block. In this paper we propose a novel block replacement scheme which considers the block reuse interval to effectively handle various data read/write patterns. The proposed scheme replaces the block in SSD based on the recency decided by reuse interval and age along with hit ratio. Computer simulation using workload trace files reveals that the proposed scheme consistently improves the performance and lifespan of SSD by increasing the hit ratio and decreasing the number of write operations compared to the existing schemes including LARC.

• Journal of the Korea Society of Computer and Information
• /
• v.18 no.11
• /
• pp.1-12
• /
• 2013

In multi-core processors, Last Level Cache(LLC) can reduce the speed gap between the memory and the core. For this reason, LLC has big impact on the performance of processors. LLC is composed of shared cache and private cache. In computer architecture community, most researchers have mainly focused on the management techniques for shared cache, while management techniques for private cache have not been widely researched. In conventional private LLC, memory is statically assigned to each core, resulting in serious performance degradation when the workloads are not fairly distributed. To overcome this problem, this paper proposes the replacement policy for managing private cache of LLC efficiently. As proposed core-aware cache replacement policy can reconfigure LLC dynamically, hit rate of LLC is increases drastically. Moreover, proposed policy uses 2-bit saturating counters to improve the performance. According to our simulation results, the proposed method can improve hit rates by 9.23% and reduce the access time by 12.85% compared to the conventional method.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.11
• /
• pp.101-109
• /
• 2009

Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.