• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.406-409
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• 2000

This paper proposes a method that enables us to implement the recursive least squares (RLS) algorithm at, high throughput rate using fewer processing elements (PEs). It is known that the pipeline processing can provide a high throughput rate. But, pipelining is effective only when enough number of PEs are available. The proposed method achieves high throughput rate using a few PEs. The effectiveness of the proposed method is verified through simulations on programmable digital signal processors (in the following, DSP processors).

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.407-418
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• 2014

As the high-throughput requirement in the next generation communication system increases, it becomes essential to implement high-throughput SISO (Soft-Input Soft-Output) decoder with minimal hardware resources. In this paper, we present the comparison results between cascaded radix-4 ACS (Add-Compare-Select) and LUT (Look-Up Table)-based radix-4 ACS in terms of delay, area, and power consumption. The hardware overhead incurred from the retiming technique used for high speed radix-4 ACS operation is also analyzed. According to the various analysis results, high-throughput radix-4 SISO decoding architecture based on simple path metric recovery circuit is proposed to minimize the hardware resources. The proposed architecture is implemented in 65 nm CMOS process and memory requirement and power consumption can be reduced up to 78% and 32%, respectively, while achieving high-throughput requirement.

• IEIE Transactions on Smart Processing and Computing
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• 제3권5호
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• pp.275-284
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• 2014

This paper considers two-tier networks consisting of macrocells and femtocells operating in the same spectrum. This paper proposes a femtocell spectrum reuse scheme that determines the shared spectrum and transmit power for the femtocells to mitigate the effects of cross-tier interference between the macrocells and femtocells. The proposed scheme provides macrocell throughput that is unaffected by the increasing number of femtocells per cell site and improves the femtocell signal quality at the same time by limiting the cross-tier interference. This study analyzed the per-tier signal-to-interference ratio (SIR) and outage probability of the proposed scheme to investigate the macrocell and femtocell performance. The total throughput of the proposed scheme was analyzed based on the outage probabilities. The analysis and numerical results proved that high femtocell throughput can be achieved using only a small fraction of the spectrum while protecting the macrocell throughput. As a result, an improved total throughput was achieved enforcing higher spatial reuse.

• 방송공학회논문지
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• 제18권4호
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• pp.535-542
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• 2013

본 논문에서는 고속 및 고인식률의 성능을 갖는 영상인식 엔진 구조를 제안한다. 본 엔진은 2단계의 특징점 추출 및 분류 알고리즘을 수행하여 자동차와 보행자를 인식할 수 있다. 엔진의 인식률을 높이기 위해 HOG 특징점 값과 LBP 특징점 값을 같이 사용하여 알고리즘을 구성하였으며, 처리 속도를 높이기 위해 병렬 구조를 개선하여 하드웨어를 설계하였다. 실험결과를 통해 설계한 엔진이 초당 90프레임의 인식 처리가 가능하며 FPPW $10^{-4}$ 하에서 97.7%의 보행자 인식률을 가짐을 보인다.

• 정보와 통신
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• 제9권9호
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• pp.72-85
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• 1992

다수의 처리 장치가 실시간 실현에 필수적이라는 것이 많은 디지털 신호처리를 일정한 시간 내에 하기 위한 요구 조건이다. VLSI 기술이 발전함으로 많은 기능 장치로 구성된 컴퓨터 시스템을 설계하고, 실현하는 것이 가능하게 되었다. 일정한 시간내에 높은 처리 능력을 갖음으로서 디지털 신호처리에 응용할 수 있는 VLSI 구조를 연구하는데 데이터 통신의 요구량과 계산의 복잡성을 최소화 할 수 있는 알고리듬의 개발이 요구된다. 이 문제를 해결하는 방법으로 DLSI 시스템이나 적응 시스템을 모델로 하는 효과적인 알고리듬을 조사하고 , 이 알고리듬을 실현할 수 있는 VLSI구조와 연관된 멀티 프로세서 시스템을 개발하는데 본 연구의 목적이 있다. 본 연구에서는 실시간 2차원 신호처리를 할 수 있는 새로운 VLSI 구조를 제안했다. 이 VLSI 구조는 칩 내부에서 단일 처리 장치가 갖는 개념을 다수의 처리 장치를 사용하는 경우로 확장하였다. 이 VLSI 구조는 입력 데이타의 크기가 증가함에 따라서 복잡성과 입력당 계산의 수가 증가하지 않는다는 장점을 갖기 때문에 매우 큰 2차원 데이타를 실시간에 처리할 수 있다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제9권3호
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• pp.886-900
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• 2015

Small cells are deployed in Heterogeneous Networks (HetNet) to improve overall performance. These access points can provide high-rate mobile services at hotspots to users. In a Small Cell Network (SCN), the good deployment of small cells can guarantee the performance of users on the basis of average and cell edge spectrum efficiency. In this paper, the performance of small cell deployment is analyzed by using system-level simulations. The positions of small cells can be adjusted according to the deployment radius and angle. Moreover, different Inter-Cell Interference Coordination (ICIC) techniques are also studied, which can be implemented either in time domain or in frequency domain. The network performances are evaluated under different ICIC techniques when the locations of Small evolved Nodes (SeNBs) vary. Simulation results show that the average throughput and cell edge throughput can be greatly improved when small cells are properly deployed with the certain deployment radius and angle. Meanwhile, how to optimally configure the parameters to achieve the potential of the deployment is discussed when applying different ICIC techniques.

• 융합신호처리학회논문지
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• 제5권3호
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• pp.216-222
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• 2004

고속 멀티미디어 전송에 있어서 주파수 선택적 페이딩은 정보 전송율 및 BER 성능에 큰 영향을 미친다. 본 논문에서는 효과적인 고속 전송을 위해 터보 부호기를 적용한 적응 QAM(Adaptive Quadrature Amplitude Modulation) 시스템을 제안한다. 친사용자 환경 시뮬레이션 플랫폼 SPW를 이용하여 터보 적응 QAM 시스템을 개발하여 주파수 선택적 채널 환경에서 수율(throughput) 및 BER 성능분석을 수행하였다. 지연 확산이 700ns와 1400ns인 두 전력 지연 프로파일을 생성시켜 수율 및 성능을 조사하였는데 지연 확산 700ns인 프로파일에서 적응 변조 시스템이 고정 QAM 변조 시스템보다 평균 0.1231 bits의 수율 향상을 얻을 수 있었고 약 3dB의 BER 성능 개선을 얻을 수 있었다. 지연 확산 1400ns인 경우에서도 적응 변조 시스템이 고정 변조 시스템보다 더 나은 BER 성능 향상을 얻을 수 있었다.

• Journal of Life Science
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• 제11권2호
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• pp.94-98
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• 2001

Type I signal peptidase cleaves the signal sequence from the amino terminus of membrane and secreted proteins afters these protein insert across the membrane. This enzyme serves as a potential target for the development of novel antibacterial agents due to its unique physiological and biochemical properties. Despite considerable research, the signal peptidase assay still remains improvement to provide further understanding of the mechanism and high-throughput inhibitor screening of this enzyme. In this paper, three known signal peptidase assays are tested with an E. coli D276A mutant signal peptidase to distinguish the sensitivity of each assays. In vitro assay using the procoat synthesized by in vitro transcription translation shows that the D276A signal peptidase I was inactive while in vivo processing of pro-OmpA expressed in the temperature-sensitive E. coli strain IT41 as well as in vitro assay using pro-OmpA nuclease A substrate show that D276A signal peptidase I has activity like wild-type signal peptidase. These results suggest that in vitro assay using the pro-OmpA nuclease A and in vivo pro-OmpA processing assay are more sensitive monitors than in vitro assay using the pro-coat. In conculsion, caution should be used when interpreting the in vitro results using the procoat.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제7권8호
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• pp.1911-1932
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• 2013

Orthogonal frequency-division multiplexing (OFDM) has become a popular modulation scheme for wireless protocols because of its spectral efficiency and robustness against multipath interference. Although the components of various OFDM protocols are functionally similar, they remain distinct because of the characteristics of the environment. Recently, graphics processing units (GPUs) have been used to accelerate the signal processing of the physical layer (PHY) because of their great computational power, high development efficiency, and flexibility. In this paper, we describe the implementation of parameterized baseband modules using GPUs for two different OFDM protocols, namely, 802.11a and 802.16. First, we introduce various modules in the modulator/demodulator parts of the transmitter and receiver and analyze the computational complexity of each module. We then describe the integration of the GPU-based baseband modules of the two protocols using the parameterized method. GPU-based implementations are addressed to explain how to accelerate the baseband processing to archive real-time throughput. Finally, the performance results of each signal processing module are evaluated and analyzed. The experiments show that the GPU-based 802.11a and 802.16 PHY meet the real-time requirement and demonstrate good bit error ratio (BER) performance. The performance comparison indicates that our GPU-based implemented modules have better flexibility and throughput to the current ones.

• ETRI Journal
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• 제42권3호
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• pp.376-387
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• 2020

Massive computation of the reconstruction algorithm for compressive sensing (CS) has been a major concern for its real-time application. In this paper, we propose a novel high-speed architecture for the orthogonal matching pursuit (OMP) algorithm, which is the most frequently used to reconstruct compressively sensed signals. The proposed design offers a very high throughput and includes an innovative pipeline architecture and scheduling algorithm. Least-squares problem solving, which requires a huge amount of computations in the OMP, is implemented by using systolic arrays with four new processing elements. In addition, a distributed-arithmetic-based circuit for matrix multiplication is proposed to counterbalance the area overhead caused by the multi-stage pipelining. The results of logic synthesis show that the proposed design reconstructs signals nearly 19 times faster while occupying an only 1.06 times larger area than the existing designs for N = 256, M = 64, and m = 16, where N is the number of the original samples, M is the length of the measurement vector, and m is the sparsity level of the signal.