• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.406-409
• /
• 2000

This paper proposes a method that enables us to implement the recursive least squares (RLS) algorithm at, high throughput rate using fewer processing elements (PEs). It is known that the pipeline processing can provide a high throughput rate. But, pipelining is effective only when enough number of PEs are available. The proposed method achieves high throughput rate using a few PEs. The effectiveness of the proposed method is verified through simulations on programmable digital signal processors (in the following, DSP processors).

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.4
• /
• pp.407-418
• /
• 2014

As the high-throughput requirement in the next generation communication system increases, it becomes essential to implement high-throughput SISO (Soft-Input Soft-Output) decoder with minimal hardware resources. In this paper, we present the comparison results between cascaded radix-4 ACS (Add-Compare-Select) and LUT (Look-Up Table)-based radix-4 ACS in terms of delay, area, and power consumption. The hardware overhead incurred from the retiming technique used for high speed radix-4 ACS operation is also analyzed. According to the various analysis results, high-throughput radix-4 SISO decoding architecture based on simple path metric recovery circuit is proposed to minimize the hardware resources. The proposed architecture is implemented in 65 nm CMOS process and memory requirement and power consumption can be reduced up to 78% and 32%, respectively, while achieving high-throughput requirement.

• IEIE Transactions on Smart Processing and Computing
• /
• v.3 no.5
• /
• pp.275-284
• /
• 2014

This paper considers two-tier networks consisting of macrocells and femtocells operating in the same spectrum. This paper proposes a femtocell spectrum reuse scheme that determines the shared spectrum and transmit power for the femtocells to mitigate the effects of cross-tier interference between the macrocells and femtocells. The proposed scheme provides macrocell throughput that is unaffected by the increasing number of femtocells per cell site and improves the femtocell signal quality at the same time by limiting the cross-tier interference. This study analyzed the per-tier signal-to-interference ratio (SIR) and outage probability of the proposed scheme to investigate the macrocell and femtocell performance. The total throughput of the proposed scheme was analyzed based on the outage probabilities. The analysis and numerical results proved that high femtocell throughput can be achieved using only a small fraction of the spectrum while protecting the macrocell throughput. As a result, an improved total throughput was achieved enforcing higher spatial reuse.

• Journal of Broadcast Engineering
• /
• v.18 no.4
• /
• pp.535-542
• /
• 2013

In this paper, we proposed a advanced hardware engine architecture for high speed and high detection rate image recognitions. We adopted the HOG-LBP feature extraction algorithm and more parallelized architecture in order to achieve higher detection rate and high throughput. As a simulation result, the designed engine which can search about 90 frames per second detects 97.7% of pedestrians when false positive per window is $10^{-4}$.

• Information and Communications Magazine
• /
• v.9 no.9
• /
• pp.72-85
• /
• 1992

The throughput requirement for many digital signal processing is such that multiple processing units are essential for real-time implementation. Advances in VLSI technology make it feasible to design and implement computer systems consisting of a large number of function units. The research on a very high throughput VLSI architecture for digital signal processing applications requires the development of an algorithm, decomposition scheme which can minimize data communication requirements as well as minimize computational complexity. The objectives of the research are to investigate computationally efficient algorithms for solution of the class of problems which can be modeled as DLSI systems or adaptive system, and develop VLSI architectures and associated multiprocessor systems which can be used to implement these algorithms in real-time. A new VLSI architecture for real-time 2-D digital signal processing applications is proposed in this research. This VLSI architecture extends the concept of having a single processing units in a chip. Because this VLSI architecture has the advantage that the complexity and the number of computations per input does not increase as the size of the input data in increased, it can process very large 2-D date in near real-time.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.9 no.3
• /
• pp.886-900
• /
• 2015

Small cells are deployed in Heterogeneous Networks (HetNet) to improve overall performance. These access points can provide high-rate mobile services at hotspots to users. In a Small Cell Network (SCN), the good deployment of small cells can guarantee the performance of users on the basis of average and cell edge spectrum efficiency. In this paper, the performance of small cell deployment is analyzed by using system-level simulations. The positions of small cells can be adjusted according to the deployment radius and angle. Moreover, different Inter-Cell Interference Coordination (ICIC) techniques are also studied, which can be implemented either in time domain or in frequency domain. The network performances are evaluated under different ICIC techniques when the locations of Small evolved Nodes (SeNBs) vary. Simulation results show that the average throughput and cell edge throughput can be greatly improved when small cells are properly deployed with the certain deployment radius and angle. Meanwhile, how to optimally configure the parameters to achieve the potential of the deployment is discussed when applying different ICIC techniques.

• Journal of the Institute of Convergence Signal Processing
• /
• v.5 no.3
• /
• pp.216-222
• /
• 2004

Frequency selective fading is a limiting factor for transmission rate and performance in high-speed multimedia communications. In this paper, we propose a turbo coded adaptive quadrature amplitude modulation (QAM) system for efficient high-speed transmission. By making use of a user-friendly simulation platform of SPW, the proposed turbo coded adaptive QAM system(TuAQAM) is developed and its performance is evaluated in terms of throughput and BER performance. Two channel models having delay spreads of 700ns and 1400ns are created for the simulations. It is shown that the proposed TuAQAM system provides a performance improvement of approximately 3dB and improved throughput for the channel model whose delay spread is 700ns. Similarly, a performance improvement is also achieved for the channel model whose delay spread is 1400ns.

• Journal of Life Science
• /
• v.11 no.2
• /
• pp.94-98
• /
• 2001

Type I signal peptidase cleaves the signal sequence from the amino terminus of membrane and secreted proteins afters these protein insert across the membrane. This enzyme serves as a potential target for the development of novel antibacterial agents due to its unique physiological and biochemical properties. Despite considerable research, the signal peptidase assay still remains improvement to provide further understanding of the mechanism and high-throughput inhibitor screening of this enzyme. In this paper, three known signal peptidase assays are tested with an E. coli D276A mutant signal peptidase to distinguish the sensitivity of each assays. In vitro assay using the procoat synthesized by in vitro transcription translation shows that the D276A signal peptidase I was inactive while in vivo processing of pro-OmpA expressed in the temperature-sensitive E. coli strain IT41 as well as in vitro assay using pro-OmpA nuclease A substrate show that D276A signal peptidase I has activity like wild-type signal peptidase. These results suggest that in vitro assay using the pro-OmpA nuclease A and in vivo pro-OmpA processing assay are more sensitive monitors than in vitro assay using the pro-coat. In conculsion, caution should be used when interpreting the in vitro results using the procoat.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.7 no.8
• /
• pp.1911-1932
• /
• 2013

Orthogonal frequency-division multiplexing (OFDM) has become a popular modulation scheme for wireless protocols because of its spectral efficiency and robustness against multipath interference. Although the components of various OFDM protocols are functionally similar, they remain distinct because of the characteristics of the environment. Recently, graphics processing units (GPUs) have been used to accelerate the signal processing of the physical layer (PHY) because of their great computational power, high development efficiency, and flexibility. In this paper, we describe the implementation of parameterized baseband modules using GPUs for two different OFDM protocols, namely, 802.11a and 802.16. First, we introduce various modules in the modulator/demodulator parts of the transmitter and receiver and analyze the computational complexity of each module. We then describe the integration of the GPU-based baseband modules of the two protocols using the parameterized method. GPU-based implementations are addressed to explain how to accelerate the baseband processing to archive real-time throughput. Finally, the performance results of each signal processing module are evaluated and analyzed. The experiments show that the GPU-based 802.11a and 802.16 PHY meet the real-time requirement and demonstrate good bit error ratio (BER) performance. The performance comparison indicates that our GPU-based implemented modules have better flexibility and throughput to the current ones.

• ETRI Journal
• /
• v.42 no.3
• /
• pp.376-387
• /
• 2020

Massive computation of the reconstruction algorithm for compressive sensing (CS) has been a major concern for its real-time application. In this paper, we propose a novel high-speed architecture for the orthogonal matching pursuit (OMP) algorithm, which is the most frequently used to reconstruct compressively sensed signals. The proposed design offers a very high throughput and includes an innovative pipeline architecture and scheduling algorithm. Least-squares problem solving, which requires a huge amount of computations in the OMP, is implemented by using systolic arrays with four new processing elements. In addition, a distributed-arithmetic-based circuit for matrix multiplication is proposed to counterbalance the area overhead caused by the multi-stage pipelining. The results of logic synthesis show that the proposed design reconstructs signals nearly 19 times faster while occupying an only 1.06 times larger area than the existing designs for N = 256, M = 64, and m = 16, where N is the number of the original samples, M is the length of the measurement vector, and m is the sparsity level of the signal.