• Title/Summary/Keyword: high-speed data communications

Search Result 327, Processing Time 0.034 seconds

Interference Minimization Using Cognitive Spectrum Decision for LED-ID Network

  • Saha, Nirzhar;Le, Nam Tuan;Jang, Yeong Min
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.38B no.2
    • /
    • pp.115-121
    • /
    • 2013
  • LED-ID (Light Emitting Diode-Identification) network is envisioned to be the next generation indoor wireless communication medium by which simultaneously high speed data transmission, identification, and illumination are possible. In spite of being extremely promising, it suffers from much impairment. Signals having different propagation paths can suffer from delays, and phase shifts which will eventually result interference. The probability of interference is also increased when communication links are established between a tag and several readers. Therefore it is necessary to reduce the interference in LED-ID network to ensure quality of service. It is possible to avoid interference by knowing the information about readers prior to assign the available spectrum. In this paper, we have proposed dynamic spectrum decision using cognitive radio concept. The simulation results justify that the proposed scheme is better than the conventional scheme.

THE DISCRETE-TIME ANALYSIS OF THE LEAKY BUCKET SCHEME WITH DYNAMIC LEAKY RATE CONTROL

  • Choi, Bong-Dae;Choi, Doo-Il
    • Communications of the Korean Mathematical Society
    • /
    • v.13 no.3
    • /
    • pp.603-627
    • /
    • 1998
  • The leaky bucket scheme is a promising method that regulates input traffics for preventive congestion control. In the ATM network, the input traffics are bursty and transmitted at high-speed. In order to get the low loss probability for bursty input traffics, it is known that the leaky bucket scheme with static leaky rate requires larger data buffer and token pool size. This causes the increase of the mean waiting time for an input traffic to pass the policing function, which would be inappropriate for real time traffics such as voice and video. We present the leaky bucket scheme with dynamic leaky rate in which the token generation period changes according to buffer occupancy. In the leaky bucket scheme with dynamic leaky rate, the cell loss probability and the mean waiting time are reduced in comparison with the leaky bucket scheme with static leaky rate. We analyze the performance of the proposed leaky bucket scheme in discrete-time case by assuming arrival process to be Markov-modulated Bernoulli process (MMBP).

  • PDF

A Study on the design of two's complement bit-serial FIR filter with systolic array architecture (Systolic Array를 이용한 Two's Complement Bit-Serial Fir 필터 설계에 관한 연구)

  • 엄두섭;박노경;차균현
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.14 no.5
    • /
    • pp.442-452
    • /
    • 1989
  • This Paper describes the impleentation of two's complement bit-serial FIR filter with systolic architectur. The filter coefficients are represented as sign and magnitude form and the input data is represented as two's complement form. We use systolic array to obtain high operation speed so this FIR filter sucessfully operates in real-time environment.

  • PDF

A design of floating-point arithmetic unit for superscalar microprocessor (수퍼스칼라 마이크로프로세서용 부동 소수점 연산회로의 설계)

  • 최병윤;손승일;이문기
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.21 no.5
    • /
    • pp.1345-1359
    • /
    • 1996
  • This paper presents a floating point arithmetic unit (FPAU) for supescalar microprocessor that executes fifteen operations such as addition, subtraction, data format converting, and compare operation using two pipelined arithmetic paths and new rounding and normalization scheme. By using two pipelined arithmetic paths, each aritchmetic operation can be assigned into appropriate arithmetic path which high speed operation is possible. The proposed normalization an rouding scheme enables the FPAU to execute roundig operation in parallel with normalization and to reduce timing delay of post-normalization. And by predicting leading one position of results using input operands, leading one detection(LOD) operation to normalize results in the conventional arithmetic unit can be eliminated. Because the FPAU can execuate fifteen single-precision or double-precision floating-point arithmetic operations through three-stage pipelined datapath and support IEEE standard 754, it has appropriate structure which can be ingegrated into superscalar microprocessor.

  • PDF

A Study on Adapted Algorithm for Local Wireless Multimedia Communication and Effective Service (근거리 무선 멀티미디어 통신망 로밍 및 효율적인 서비스에 적합한 알고리즘 연구)

  • Kang Jung yong;Lee Seon keun;Kim Hwan yong
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.29 no.12A
    • /
    • pp.1349-1355
    • /
    • 2004
  • In tile wireless communication networks although the modulation and demodulation structure with proposed BOWLIS algorithm is a little confusing but we certified that it is fit structure in fast operation processing and high speed wireless LAM system that is more strong on frequence and electro magnetic interference because it process the inputted data within 2.8Us that is faster 0.4Us than 3.2Us in standard form. Also we certified that in the sigtlt of consuming power it is better than pipe-lined structure because of reducing the processing step to 4.

Design of Core Chip for 3.1Gb/s VCSEL Driver in 0.18㎛ CMOS (0.18㎛ CMOS 3.1Gb/s VCSEL Driver 코아 칩 설계)

  • Yang, Choong-Reol;Lee, Sang-Soo
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.38A no.1
    • /
    • pp.88-95
    • /
    • 2013
  • We propose a novel driver circuit design using $0.18{\mu}m$ CMOS process technology that drives a 1550 nm high-speed VCSEL used in optical transceiver. We report a distinct improvement in bandwidth, voltage gain and eye diagram at 3.1Gb/s data rate in comparison with existing topology. In this paper, the design and layout of a 3.1Gb/s VCSEL driver for optical transceiver having arrayed multi-channel of integrating module is confirmed.

Signal Space Representation of Half-Symbol-Rate-Carrier PSK Modulations

  • Yeo, Hyeop-Goo
    • Journal of information and communication convergence engineering
    • /
    • v.7 no.3
    • /
    • pp.304-308
    • /
    • 2009
  • This paper proposes a new concept of a signal constellation of the recently introduced half-symbol-rate-carrier phase-shift keying (HSRC-PSK) modulations for bandwidth-efficient high speed data communications. Since the HSRC-PSK modulations contain different symbol energies representing the same bit sequences due to the loss of orthogonality of their HSRC signals, it is very hard to represent the symbol using the conventional signal constellation. To resolve the problem, two different energies are assigned to represent one symbol for the HSRC offset quadrature phase shift keying (OQPSK) modulation. Similarly, the different energies exist to display the different symbol for HSRC minimum shift keying (MSK) modulation. With the proposed signal space representation, HSRC-PSK symbol can easily be shown with a two-dimensional scatter plot which provides helpful information of evaluating HSRC-PSK signal's quality.

Multiple LC-tries for Fast IP Address Lookup (고속 IP 주소 검색을 위한 다중 LC-트라이)

  • 황현숙;권택근
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.26 no.11C
    • /
    • pp.43-50
    • /
    • 2001
  • The IP routing uses the longest-matching prefix to determine the destination. Fast lookup should be required for the high speed routing. We propose a modified LC-trie, called multiple LC-trie, which is suitable data structure for fast address-lookups in software implementation. To reduce the number of memory accesses, our scheme analyzes the distribution of IP address access pattern, and constructs multiple LC:-tries for frequently accessed IP addresses. Our experimental results show that our scheme can perform faster than the original LC-trie schemes.

  • PDF

Development of a Wireless Video Transmitter for Automobile Camera System based on the Binary-CDMA Technology (Binary CDMA 기반 차량용 카메라 시스템의 무선 영상전송기 개발)

  • Choi, Jae-Won
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.18 no.7
    • /
    • pp.1571-1578
    • /
    • 2014
  • Binary CDMA is a new standard technology for wireless communication developed by our country that makes high speed communications and good quality of services for multimedia data such as voice and video. In this paper we researched the design and implementation of a wireless Video Transmitter and Video Server - the main devices for the Automobile Wireless Camera System - based on the Binary-CDMA technology that makes them freely installed in any place without wired cables restriction.

A Study on Implementation of the Statistical Multiplexer for ISDN D-channel (ISDN D채널 다중화를 위한 총계적 다중화기의 실현에 관한 연구)

  • 박정호;김영철;이호준;조규섭;박병철;김병찬
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.12 no.2
    • /
    • pp.102-114
    • /
    • 1987
  • In this paper, in order to develop the transmission system between the remote subscriber and the central office, the hardware and software implementation of a SMUX(Statistical Multiplexer)which can interleace eleven 16Kbps D-channels over a 64Kbps B-channel is obtained. As a result of this study, the high speed data transmission by the use of a dynamic buffer memory management algofithm for statistical multiplexing is realized. Especially a software architectur for interruption is proposed in order to improve performance of the transmission system more efficiently.

  • PDF