• Title/Summary/Keyword: high switching frequency

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Research on Power Converters for High-Efficient and Light-Weight Auxiliary Power Supplies (APS) in Railway System (철도차량 보조전원장치의 고효율-경량화를 위한 전력변환회로 연구)

  • Lee, Jae-Bum;Cho, In-Ho
    • Journal of the Korean Society for Railway
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    • v.20 no.3
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    • pp.329-338
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    • 2017
  • A recent trend of technical development in auxiliary-power-supplies (APS) is to replace 60Hz low frequency transformers with isolated type dc/dc converters. This paper introduces the technical trend in APS structures and proposes a power converter circuit suitable for high-efficient and light-weight APS. By utilizing the resonant converter, which achieves ZCS, to reduce switching losses, various types of APS structures (1-stage and 2-stage) are reviewed, and they are verified by simulation. The full-bridge resonant LLC converter is designed with a 1-stage power converting structure; the resonant converter topology is designed with a 2-stage power converting structure that has a pre-regulator converter to compensate for the wide input voltage range. Both a step-down converter and a step-up converter are designed and compared for the pre-regulator in the 2-stage structure. Operational characteristics are compared with simulation results and loss analyses are presented to proposes appropriate system structure and topologies.

Implementation of the BLDC Motor Drive System using PFC converter and DTC (PFC 컨버터와 DTC를 이용한 BLDC 모터의 구동 시스템 구현)

  • Yang, Oh
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.44 no.5
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    • pp.62-70
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    • 2007
  • In this paper, the boost Power Factor Correction(PFC) technique for Direct Torque Control(DTC) of brushless DC motor drive in the constant torque region is implemented on a TMS320F2812DSP. Unlike conventional six-step PWM current control, by properly selecting the inverter voltage space vectors of the two-phase conduction mode from a simple look-up table at a predefined sampling time, the desired quasi-square wave current is obtained, therefore a much faster torque response is achieved compared to conventional current control. Furthermore, to eliminate the low-frequency torque oscillations caused by the non-ideal trapezoidal shape of the actual back-EMF waveform of the BLDC motor, a pre-stored back-EMF versus position look-up table is designed. The duty cycle of the boost converter is determined by a control algorithm based on the input voltage, output voltage which is the dc-link of the BLDC motor drive, and inductor current using average current control method with input voltage feed-forward compensation during each sampling period of the drive system. With the emergence of high-speed digital signal processors(DSPs), both PFC and simple DTC algorithms can be executed during a single sampling period of the BLDC motor drive. In the proposed method, since no PWM algorithm is required for DTC or BLDC motor drive, only one PWM output for the boost converter with 80 kHz switching frequency is used in a TMS320F2812 DSP. The validity and effectiveness of the proposed DTC of BLDC motor drive scheme with PFC are verified through the experimental results. The test results verify that the proposed PFC for DTC of BLDC motor drive improves power factor considerably from 0.77 to as close as 0.9997 with and without load conditions.

A 10-bit 100 MSPS CMOS D/A Converter with a Self Calibration Current Bias Circuit (Self Calibration Current Bias 회로에 의한 10-bit 100 MSPS CMOS D/A 변환기의 설계)

  • 이한수;송원철;송민규
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.11
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    • pp.83-94
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    • 2003
  • In this paper. a highly linear and low glitch CMOS current mode digital-to-analog converter (DAC) by self calibration bias circuit is proposed. The architecture of the DAC is based on a current steering 6+4 segmented type and new switching scheme for the current cell matrix, which reduced non-linearity error and graded error. In order to achieve a high performance DAC . novel current cell with a low spurious deglitching circuit and a new inverse thermometer decoder are proposed. The prototype DAC was implemented in a 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. Experimental result show that SFDR is 60 ㏈ when sampling frequency is 32MHz and DAC output frequency is 7.92MHz. The DAC dissipates 46 mW at a 3.3 Volt single power supply and occupies a chip area of 1350${\mu}{\textrm}{m}$ ${\times}$750${\mu}{\textrm}{m}$.

Omnichannel's Perception Effect on Omnichannel Use and Customer-Brand Relationship (옴니채널의 지각된 편리성과 유용성이 옴니채널 사용과 소비자-브랜드 관계에 미치는 영향)

  • Yim, Duk-Soon;Han, Sang-Seol
    • Journal of Distribution Science
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    • v.14 no.7
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    • pp.83-90
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    • 2016
  • Purpose - This study focuses on new type distribution channel that named as Omnichannel. Omnichannel is developed from Multichannel which is used in many distribution channels to buy or selling goods. Omnichannel basically needs an Information and Communications Technologies(ICT) to use, so researcher conduct a Technology Acceptance Model(TAM) to research model. Customer-brand relationship was used as dependent variable to focus on the role of Omnichannel. Research design, data, and methodology - The subject of this study is customer who purchase goods or service through omnichannel. Based on the literature from the preceding research analysis of TAM and customer-brand relationship, this study was constructed by the reference to previous studies, final research model design for figure out casual relationship among perceived ease of use, perceived usefulness, omnichannel use and customer-brand relationship. From 2016 February 3 to March 17, questionnaire survey targeted customers who use online and offline channels. 273 questionnaire survey had conducted, then, 252 survey data were available for empirical analysis. Researcher provide descriptive statistics for checking generality. Cronbach's alpha value was used to check the reliability of data. Exploratory factor analysis was used for purification of values and eigenvalue checking. After EFA, Confirmatory factor analysis was used to prepare structural equation modeling with executing structural equation modeling for confirming hypothesis which developed by researcher. Results - The main results of this empirical study are as follows. First, omnichannel's perceived ease of use has positive significant effect on perceived usefulness(estimate: 0.579). Moreover, omnichannel's perceived ease of use and perceived usefulness has positive significant effect on omnichannel use(estimate: 0.325,0.648). Second, using omnichannel has positive significant effect on brand-customer relationship(estimate: 0.521). Every hypothesis adopted as researcher designed. This study found out the intermediate relationship between perceived ease of use and omnichannel use by investigating hypothesis. Conclusions - Base on the empirical result, this study confirmed that TAM theory perceived has relation with omnichannel. First, factors of TAM has positive effect on omnichannel use, so it highlights the important role of customer based interface and usefulness. Especially, perceived usefulness has high indirect influence on ease of use and use of omnichannel. It seems that when customers try to decide use or not use omnichannel, customers focus on percept benefits from omnichannel. Thus, a provider should applicate attractive price table, accurate product or service information and high switching cost strategy to emphasize the usefulness of omnichannel. Second, using omnichannel enhances the relationship between customers and brand, because there are more time and frequency to serve customers. It is important because good relationship between customers can increase the future's financial performance through word of mouse, positive brand image and loyalty to brand or company. Finally, despite of empirical result and implications, this study has limitations. First, there are only a few previous studies about omnicahnnel, so literature reviews are restricted. While set up the factors which can affect the use of omnichannel, next study should be considered with broader theories or models(ex: contingency theory). Second, omnichannel has developed from multichannel, so comparative analysis is needed between these methods because there is a possibility about different forte character of each distribution system on customer's consuming patterns.

Structure and Control of Smart Transformer with Single-Phase Three-Level H-Bridge Cascade Converter for Railway Traction System (Three-Level H-Bridge 컨버터를 이용한 철도차량용 지능형 변압기의 구조 및 제어)

  • Kim, Sungmin;Lee, Seung-Hwan;Kim, Myung-Yong
    • Journal of the Korean Society for Railway
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    • v.19 no.5
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    • pp.617-628
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    • 2016
  • This paper proposes the structure of a smart transformer to improve the performance of the 60Hz main power transformer for rolling stock. The proposed smart transformer is a kind of solid state transformer that consists of semiconductor switching devices and high frequency transformers. This smart transformer would have smaller size than the conventional 60Hz main transformer for rolling stock, making it possible to operate AC electrified track efficiently by power factor control. The proposed structure employs a cascade H-Bridge converter to interface with the high voltage AC single phase grid as the rectifier part. Each H-Bridge converter in the rectifier part is connected by a Dual-Active-Bridge (DAB) converter to generate an isolated low voltage DC output source of the system. Because the AC voltage in the train system is a kind of medium voltage, the number of the modules would be several tens. To control the entire smart transformer, the inner DC voltage of the modules, the AC input current, and the output DC voltage must be controlled instantaneously. In this paper, a control algorithm to operate the proposed structure is suggested and confirmed through computer simulation.

A Nulling Anti-Jamming Scheme for the Polyphase Filter Bank-Based Satellite Repeat System (다상 필터 뱅크 기반의 위성 중계시스템을 위한 항재밍 기법의 연구)

  • Oh, Jin-O;Im, Sung-Bin;Ko, Hyun-Suk
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.49 no.7
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    • pp.39-47
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    • 2012
  • The combination of the broadband property and the wide area coverage of satellite communications enables high speed transmission. Every user in the region under the satellite beam coverage can tranceiver and one can simultaneously communicate with multiple users. For these reasons, it is one of commendable telecommunication networks for information transfer. Since the satellite communications use open channels, it is likely to cause jamming with unwanted interference signals. In the thesis, APSK (Amplitude Phase Shift Keying) is employed, which is recommended for DVB-S2 due to high-speed transmission and excellent bandwidth efficiency. For obtaining reliable communication under the jamming environments, the communication satellite transponder rests on the polyphase filter bank structure, which enables switching among the subchannels and gain control on each subchannel, resulting in effectively eliminating jamming. Furthermore, the nulling scheme, one of the various anti-jamming approaches, is investigated, in which unwanted jamming signals are eliminated in the frequency domain after passing through the analysis part of the polyphase filter bank. The performance of the nulling scheme is evaluated for tone jamming and partial band jamming in terms of BER and EVM. The simulation results indicate that the nulling scheme improve the BER and EVM performance over the case without any anti-jamming approach.

Design of X-Band High Efficiency 60 W SSPA Module with Pulse Width Variation (펄스 폭 가변을 이용한 X-대역 고효율 60 W 전력 증폭 모듈 설계)

  • Kim, Min-Soo;Koo, Ryung-Seo;Rhee, Young-Chul
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.9
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    • pp.1079-1086
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    • 2012
  • In this paper, X-band 60 W Solid-State Power Amplifier with sequential control circuit and pulse width variation circuit for improve bias of SSPA module was designed. The sequential control circuit operate in regular sequence drain bias switching of GaAs FET. The distortion and efficiency of output signals due to SSPA nonlinear degradation is increased by making operate in regular sequence the drain bias wider than that of RF input signals pulse width if only input signal using pulsed width variation. The GaAs FETs are used for the 60 W SSPA module which is consists of 3-stage modules, pre-amplifier stage, driver-amplifier stage and main-power amplifier stage. The main power amplifier stage is implemented with the power combiner, as a balanced amplifier structure, to obtain the power greater than 60 W. The designed SSPA modules has 50 dB gain, pulse period 1 msec, pulse width 100 us, 10 % duty cycle and 60 watts output power in the frequency range of 9.2~9.6 GHz and it can be applied to solid-state pulse compression radar using pulse SSPA.

A Non-Calibrated 2x Interleaved 10b 120MS/s Pipeline SAR ADC with Minimized Channel Offset Mismatch (보정기법 없이 채널 간 오프셋 부정합을 최소화한 2x Interleaved 10비트 120MS/s 파이프라인 SAR ADC)

  • Cho, Young-Sae;Shim, Hyun-Sun;Lee, Seung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.9
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    • pp.63-73
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    • 2015
  • This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.

Design and Implementation of Digital Electrical Impedance Tomography System (디지털 임피던스 영상 시스템의 설계 및 구현)

  • 오동인;백상민;이재상;우응제
    • Journal of Biomedical Engineering Research
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    • v.25 no.4
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    • pp.269-275
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    • 2004
  • Different biological tissues have different values of electrical resistivity. In EIT (electrical impedance tomography), we try to provide cross-sectional images of a resistivity distribution inside an electrically conducting subject such as the human body mainly for functional imaging. However, it is well known that the image reconstruction problem in EIT is ill-posed and the quality of a reconstructed image highly depends on the measurement error. This requires us to develop a high-performance EIT system. In this paper, we describe the development of a 16-channel digital EIT system including a single constant current source, 16 voltmeters, main controller, and PC. The system was designed and implemented using the FPGA-based digital technology. The current source injects 50KHz sinusoidal current with the THD (total harmonic distortion) of 0.0029% and amplitude stability of 0.022%. The single current source and switching circuit reduce the measurement error associated with imperfect matching of multiple current sources at the expense of a reduced data acquisition time. The digital voltmeter measuring the induced boundary voltage consists of a differential amplifier, ADC, and FPGA (field programmable gate array). The digital phase-sensitive demodulation technique was implemented in the voltmeter to maximize the SNR (signal-to-noise ratio). Experimental results of 16-channel digital voltmeters showed the SNR of 90dB. We used the developed EIT system to reconstruct resistivity images of a saline phantom containing banana objects. Based on the results, we suggest future improvements for a 64-channel muff-frequency EIT system for three-dimensional dynamic imaging of bio-impedance distributions inside the human body.

A Study on Efficiency Improvement of X-Band Power Amplifier Using Harmonic Control Circuit (고조파 제어 회로를 이용한 X-대역 전력 증폭기의 효율 개선에 관한 연구)

  • Kim, Hyoung-Jong;Choi, Jin-Joo;Kim, Dong-Yoon;Na, Hyung-Gi
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.9
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    • pp.987-994
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    • 2010
  • In this paper, a simple and effective active load-pull method is proposed, and the method to improve the efficiency of X-band power amplifier using harmonic control circuit is presented. The proposed active load-pull system mainly consists of directional coupler, phase shifter, short circuit, and power amplifier, and allows a user to access reflection coefficients near the edge of the Smith chart($\Gamma$=1) easily. The device used in this paper is Mitsubishi's GaAs FET MGF1801, and the operating frequency of the power amplifier is 9 GHz, The amplifier had output power of 21.65 dBm and drain efficiency of 24.9 % at class-A, and had output power of 21.46 dBm and drain efficiency of 53.3 % at class-AB. Harmonic control circuit is designed only second and third harmonic components because of the bandwidth limitation of the microwave components. The drain efficiency is improved as much as 6.4 % compared with class-AB power amplifier.