• 한국전기전자재료학회논문지
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• 제22권9호
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• pp.737-740
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• 2009

SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics, In this paper, we demonstrated that the switching performance of DMOSFETs are dependent on the with Channel length ($L_{channel}$) and Current Spreading Layer thickness ($T_{CSL}$) by using 2-D Mixed-mode simulations. The 4H-SiC DMOSFETs with a JFET region designed to block 800 V were optimized for minimum loss by adjusting the parameters of the JFET region, CSL, and epilayer. It is found that improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance. Therefore, accurate modeling of the operating conditions are essential for the optimizatin of superior switching performance.

• 인터넷정보학회논문지
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• 제8권5호
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• pp.161-170
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• 2007

본 논문은 데이터 메모리 평면과 스위칭 평면을 분리하여 패킷 데이터의 저장과 메모리 주소 포인터의 스위칭이 병렬적으로 처리 가능하며 IP 패킷의 가변 길이 스위칭이 가능한 새로운 스위치 구조를 제안한다. 제안한 구조는 기존 VOQ방식의 복잡한 중재 알고리즘이 필요 없으며 출력 큐 방식의 스위치에서만 적용되고 있는 QoS를 입력 큐에서 고려한다. 성능분석 결과 제안한 구조는 기존의 공유 메모리 기반의 구조들에 비해 상대적으로 낮은 평균 지연 시간을 가지며 스위치의 크기가 증가하더라도 일정한 지연 시간을 보장함을 확인하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 추계학술대회 논문집 학회본부
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• pp.156-158
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• 1994

In recent days, the various adjustable speed drives are widely employed at the industrial applications for the purpose of energy saving and speed control. In particular, for the machine control applications. the switching frequency is required to be increased for better dynamic performance of the drive. Moreover, this also leads to the reduction of the switching loss of the device. For IGBT (Insulated Gate Bipolar Transistor), the most widely used switching device in the inverters below the 100[kW] range, the falling and falling time is of the order about $200{\sim}300[ns]$. Therefore unexpected phenomena occurs such as voltage spikes due to high gradient of current at the switching instant, the weakening of motor insulation due to high gradient of voltage. In this paper, a new voltage gradient suppression technique is presented in both theoretically and experimentally.

• 전력전자학회논문지
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• 제5권6호
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• pp.530-536
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• 2000

• International Journal of Precision Engineering and Manufacturing
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• 제2권1호
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• pp.33-42
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• 2001

In switched reluctance motor(SRM) deives, the turn-on and turn-off angles of each phase switch should be accurately controlled for accuracy and efficiency. The accuracy of the switching angles is mainly dependent upon the resolution of the encoder and the sampling period of the microprocessor, that are used to provide the information of the rotor position and to implement a control algorithm of the SRM, respectively. Thus, the higher the speed of the SRM is increased, the larger the amount of the switching angle deviations are from preset turn-on and turn-off angles. Consequently, the motor can not be driven stably high speed region. There fore, a simples and low cost encoder suitable for the practical and stable SRM drive is proposed and the control algorithm to provide the switching signals using a simple digital logic circuit is also presented for a wide speed range operation.

• 전기학회논문지P
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• 제57권2호
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• pp.72-78
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• 2008

The speed variation of SRM is fulfilled throughout a transition from chopping control to single pulse operation. (i,e., low speed to high speed operation). It is unsatisfied with performance at all operational regimes. In this paper, the operational performance of SRM can be improved by using current hysteresis control method. This method maintains a generally flat current waveform. At the high speed, the current chopping capability is lost due to the development of the back-EMF. Therefore SRM operates in single pulse mode. By using zero-current switching and zero-voltage switching technique, the stress of power switches can be reduce in chopping mode. When the commutation from one phase winding to another phase winding, the current can be zero as fast as possible in this period because several times negative voltage of DC-source voltage produce in phase winding. This paper is compared to performance based on conventional C-dump converter topology and the proposed resonant C-dump converter topology. Simulation and experimental results are presented to verify the effectiveness of the proposed circuit.

• 정보처리학회논문지C
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• 제11C권4호
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• pp.527-538
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• 2004

본 논문에서는 MPLS에서 전체 플로우의 수를 줄이고 확장성(scalability) 문제를 해결할 수 있는 테이블 관리 방안으로서 플로우 집적화와 플로우 유지 시간 제어 알고리즘을 제안하였다. 목적지 주소 기반 플로우 집적화 방식은 인터넷에서 전체 플로우의 수를 감소시키고 레이블을 효율적으로 사용할 수 있도록 관리하여 전체 패킷의 스위칭 비율을 향상시킬 수 있는 방식이며, 플로우 유지 시간 제어 알고리즘은 불필요한 플로우에게 할당되어 있는 레이블을 가능한 빨리 해제함으로써 레이블의 과도한 낭비를 줄일 수 있는 방법이다. 본 논문에서는 실제 인터넷 트래픽 트레이스를 이용하여 시뮬레이션을 수행함으로써 제안한 두 가지 방식의 성능을 검증하였다. 성능검증에서는 레이블 사용 효율, 평균 fp이블 사용량, 그리고 스위칭 된 패킷수와 스위칭 된 비율을 이용하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.105-108
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• 1999

In this paper, we define the high-speed router as a router, which can support aggregated ports over 25Gbps, and provide issues and trends in high-speed router design. We propose design considerations on IP packet forwarding, switching fabric, packet scheduling and buffer management, network resource reservation, and router operation and administration.

• 대한전기학회논문지
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• 제43권7호
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• pp.1075-1083
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• 1994

In this paper, a study on the improvement of the IM speed response against load torque variation is presented. A VSCS(Variable Structure Control System) is proposed which gives the desired robustness against load torque variation using a new kind of time-varing switching plane. In order to eliminate the reaching phase of the states from one switching plane to another during variation, the switching plane is varied continuously. To verify the high dynamic performance of the proposed VSCS, simulation and experimental results are presented.

• ETRI Journal
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• 제31권3호
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• pp.342-344
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• 2009

From a hydrodynamic device simulation for the pseudomorphic high electron mobility transistors (pHEMTs), we observe an increase of maximum extrinsic transconductance and a decrease of source-drain capacitances. This gives rise to an enhancement of the switching speed and isolation characteristics as the upper-to-lower planar-doping ratios (UTLPDR) increase. On the basis of simulation results, we fabricate single-pole-double-throw transmitter/receiver monolithic microwave integrated circuit (MMIC) switches with the pHEMTs of two different UTLPDRs (4:1 and 1:2). The MMIC switch with a 4:1 UTLPDR shows about 2.9 dB higher isolation and approximately 2.5 times faster switching speed than those with a 1:2 UTLPDR.