• Restorative Dentistry and Endodontics
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• v.26 no.5
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• pp.393-398
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• 2001

Polymerization of light-activated restorations results in temperature increase caused by both the exothermic reaction process and the energy absorbed during irradiation. Within composite resin, temperature increases up to 2$0^{\circ}C$ or more during polymerization. But, insulation of hard tissue of tooth lowers this temperature increase in pulp. However, many clinicians are concerned about intrapulpal temperature injury. The purpose of this study was to evaluate temperature changes in the pulp according to various restorative materials and bases during curing procedure. Caries and restoration-free mandibular molars extracted within three months were prepared Class I cavity of 3$\times$6mm with high speed handpiece fissure bur. 1mm depth of dentin was evaluated with micrometer in mesial and distal pulp horns. Pulp chambers were filled with 37.0$\pm$0.1$^{\circ}C$ water to CEJ. Chromium-alumina thermocouple was placed in pulp horn below restorative materials for evaluating of temperature changes. This thermocouple was connected to temperature-recording device(Multiplication analyzer MX, 6.000, JAPAN). Temperature changes was evaluated from initial 37.$0^{\circ}C$ after temperature changes to 37.$0^{\circ}C$. Tip of curing unit was placed in the center of prepared cavity separated 1mm from restorative materials. Curing time was 40s. The restorative materials were used with Z 100, Fuji II LC, Compoglass flow and bases were used with Vitrebond, Dycal. Resrorative materials were placed in 2mm. The depth of bases were formed in 1mm and in this upper portion, resin of 2mm depth was placed. This procedure was performed 10 times. The results were as follows. 1. All the groups showed that the temperature in pulp increased as curing time increased 2. The temperature increase of glass ionomer was significantly higher than that of Resin and Compomer during curing procedure (P<0.05). 3. The temperature increase in glass ionomer base was significantly higher than that of Calcium hydroxide base during Resin curing procedure (P<0.05).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2052-2058
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• 2009

As the operating frequency of digital system increases and voltage swing decreases, an accurate and high speed analysis of PCB board becomes very important. Transmission matrix method, which use the multiple products of unit column matrix, is the highest speedy method in PCB board analysis. In this paper a new method to reduce the calculation time of PCB board impedances is proposed. First, in this method the eigenvalue and eigenvectors of the transmission matrix for unit column of PCB are calculated and the transmission matrix for the unit column is transformed using similarity transform to reduce the number of multiplication on the matrix elements. This method using the similarity transform can reduce the calculation time greatly comparing the previous method. The proposed method is applied to the 1.3 inch by 1.9 inch board and shows about 10 times reduction of calculation time. This method can be applied to the PCB design which needs a lots of repetitive calculation of board impedances.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.3
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• pp.165-171
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• 2019

The study of the computer architecture has shown that major improvements in price-to-energy performance stems from domain-specific hardware development. This paper analyzes the tensor processing unit (TPU) ASIC which can accelerate the reasoning of the artificial neural network (NN). The core device of the TPU is a MAC matrix multiplier capable of high-speed operation and software-managed on-chip memory. The execution model of the TPU can meet the reaction time requirements of the artificial neural network better than the existing CPU and the GPU execution models, with the small area and the low power consumption even though it has many MAC and large memory. Utilizing the TPU for the tensor flow benchmark framework, it can achieve higher performance and better power efficiency than the CPU or CPU. In this paper, we analyze TPU, simulate the Python modeled OpenTPU, and synthesize the matrix multiplication unit, which is the key hardware.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.1
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• pp.55-60
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• 2021

This paper relates with the performance evaluation of QE-MMA (Quantized Error-MMA) adaptive equalization algorithm based on the stepsize and quantizer bit number in order to reduce the intersymbol interference due to nonlinear distortion occurred in the time dispersive channel. The QE-MMA was proposed using the power-of-two arithmetic for the H/W implementation easiness substitutes the multiplication and addition into the shift and addition in the tap coefficient updates process that modifies the SE-MMA which use the high-order statistics of transmitted signal and sign of error signal. But it has different adaptive equalization performance by the step size and quantizer bit number for obtain the sign of error in the generation of error signal in QE-MMA, and it was confirmed by computer simulation. As a simulation, it was confirmed that the convergence speed for reaching steady state depend on stepsize and the residual quantities after steady state depend on the quantizer bit number in the QE-MMA adaptive equalization algorithm performance.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.4
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• pp.81-93
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• 2000

In a methodological approach to improve the processing performance of modulo exponentiation which is the primary arithmetic in RSA crypto algorithm, we present a new RSA hardware architecture based on high-radix modulo multiplication and CRT(Chinese Remainder Theorem). By implementing the modulo multiplier using radix-16 arithmetic, we reduced the number of PE(Processing Element)s by quarter comparing to the binary arithmetic scheme. This leads to having the number of clock cycles and the delay of pipelining flip-flops be reduced by quarter respectively. Because the receiver knows p and q, factors of N, it is possible to apply the CRT to the decryption process. To use CRT, we made two s/2-bit multipliers operating in parallel at decryption, which accomplished 4 times faster performance than when not using the CRT. In encryption phase, the two s/2-bit multipliers can be connected to make a s-bit linear multiplier for the s-bit arithmetic operation. We limited the encryption exponent size up to 17-bit to maintain high speed, We implemented a linear array modulo multiplier by projecting horizontally the DG of Montgomery algorithm. The H/W proposed here performs encryption with 15Mbps bit-rate and decryption with 1.22Mbps, when estimated with reference to Samsung 0.5um CMOS Standard Cell Library, which is the fastest among the publications at present.

• KIPS Transactions on Computer and Communication Systems
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• v.6 no.3
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• pp.105-112
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• 2017

PCI Express is a bus technology that connects the processor and the peripheral I/O devices that widely used as an industry standard because it has the characteristics of high-speed, low power. In addition, PCI Express is system interconnect technology such as Ethernet and Infiniband used in high-performance computing and computer cluster. PGAS(partitioned global address space) programming model is often used to implement the one-sided RDMA(remote direct memory access) from multi-host systems, such as computer clusters. In this paper, we design and implement a OpenSHMEM API based on PCI Express maintaining the existing features of OpenSHMEM to implement RDMA based on PCI Express. We perform experiment with implemented OpenSHMEM API through a matrix multiplication example from system which PCs connected with NTB(non-transparent bridge) technology of PCI Express. The PCI Express interconnection network is currently very expensive and is not yet widely available to the general public. Nevertheless, we actually implemented and evaluated a PCI Express based interconnection network on the RDK evaluation board. In addition, we have implemented the OpenSHMEM software stack, which is of great interest recently.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.21-34
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• 2002

In this paper we propos a new hardware architecture of modular exponentiation using a division chain method which has been proposed in (2). Modular exponentiation using the division chain is performed by receding an exponent E as a mixed form of multiplication and addition with divisors d=2 or $d=2^I +1$ and respective remainders r. This calculates the modular exponentiation in about $1.4log_2$E multiplications on average which is much less iterations than $2log_2$E of conventional Binary Method. We designed a linear systolic array multiplier with pipelining and used a horizontal projection on its data dependence graph. So, for k-bit key, two k-bit data frames can be inputted simultaneously and two modular multipliers, each consisting of k/2+3 PE(Processing Element)s, can operate in parallel to accomplish 100% throughput. We propose a new encoding scheme to represent divisors and remainders of the division chain to keep regularity of the data path. When it is synthesized to ASIC using Samsung 0.5 um CMOS standard cell library, the critical path delay is 4.24ns, and resulting performance is estimated to be abort 140 Kbps for a 1024-bit data frame at 200Mhz clock In decryption process, the speed can be enhanced to 560kbps by using CRT(Chinese Remainder Theorem). Futhermore, to satisfy real time requirements we can choose small public exponent E, such as 3,17 or $2^{16} +1$, in encryption and verification process. in which case the performance can reach 7.3Mbps.