• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.255-255
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• 2010

Recently, nonvolatile memories (NVM) of various types have been researched to improve the electrical performance such as program/erase voltages, speed and retention times. Also, the charge trap memory is a strong candidate to realize the ultra dense 20-nm scale NVM. Furthermore, the high charge efficiency and the thermal stability of SiC nanocrystals NVM with single $SiO_2$ tunnel barrier have been reported. [1-2] In this study, the SiC charge trap NVM was fabricated and electrical properties were characterized. The 100-nm thick Poly-Si layer was deposited to confined source/drain region by using low-pressure chemical vapor deposition (LP-CVD). After etching and lithography process for fabricate the gate region, the $Si_3N_4/SiO_2/Si_3N_4$ (NON) and $SiO_2/Si_3N_4/SiO_2$ (ONO) barrier engineered tunnel layer were deposited by using LP-CVD. The equivalent oxide thickness of NON and ONO tunnel layer are 5.2 nm and 5.6 nm, respectively. By using ultra-high vacuum magnetron sputtering with base pressure 3x10-10 Torr, the 2-nm SiC and 20-nm $SiO_2$ were successively deposited on ONO and NON tunnel layers. Finally, after deposited 200-nm thick Al layer, the source, drain and gate areas were defined by using reactive-ion etching and photolithography. The lengths of squire gate are $2\;{\mu}m$, $5\;{\mu}m$ and $10\;{\mu}m$. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer, E4980A LCR capacitor meter and an Agilent 81104A pulse pattern generator system. The electrical characteristics such as the memory effect, program/erase speeds, operation voltages, and retention time of SiC charge trap memory device with barrier engineered tunnel layer will be discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.252-255
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• 2004

반도체는 high integrated, high speed, low power를 위하여 design 뿐만 아니라 재료 측면에서도 많은 변화를 가져오고 있으며, RC delay time을 줄이기 위하여 Al 배선보다 비저항이 낮은 Cu와 low-k material 적용이 그 대표적인 예이다. 그러나, Cu 배선의 경우 dry etching이 어려우므로, 기존의 공정으로는 그 한계를 가지므로 damascene 또는 dual damascene 공정이 소개, 적용되고 있다. Damascene 공정은 절연막에 photo와 RIE 공정을 이용하여 trench를 형성시킨 후 electrochemical plating 공정을 이용하여 trench에 Cu를 filling 시킨다. 이후 CMP 공정을 이용하여 절연막 위의 Cu와 barrier material을 제거함으로서 Cu 배선을 형성하게 된다. Dual damascene 공정은 trench와 via를 동시에 형성시키는 기술로 현재 대부분의 Cu 배선 공정에 적용되고 있다. Cu CMP는 기존의 metal CMP와 마찬가지로 oxidizer를 이용한 Cu film의 화학반응과 연마 입자의 기계가공이 기본 메커니즘이다. Cu CMP에서 backside pressure 영향이 uniformity에 미치는 영향을 살펴보았으며, electrochemical plating 공정에서 발생하는 hump가 CMP 결과에 미치는 영향과 dishing 결과를 통하여 그 영향을 평가하였다.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.11
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• pp.575-580
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• 2001

In this paper, using $500\mum-thickness\; (100)\; silicon\; wafer,\; flat\; 65\mum-thickness$ silicon mirror plates were fabricated through dry etching and wet etching, and $45\mum-depth$ grooved driving electrodes were fabricated through UV-LIGA process. Four shapes of the driving electrode were fabricated: twenty four grooves of the $50\mum-width$, twelve grooves of the $100\mum-width$, six grooves of the $200\mum-width$, and no grooves on the driving electrode. Fabricated mirror plate size and spring size are $2400\times2400\times65\mum3\; and \;500\times10\times65\mum3,$ respectively. Mirror plate parts and driving electrodes were assembled into the scanning mirrors. Measured natural resonance frequencies were about 600Hz which have error within $\pm 2%$ to calculated value. Due to the squeeze effect in the narrow gap between the mirror plate and the driving electrode, measured resonance frequencies were reduced as raising the amplitude of the mirror plate. In a case of driving electrode without grooves, the resonance frequency was reduced largely, compared with a case of driving electrode with grooves. According to the experimental results, squeeze effect was smaller in the driving electrode with smaller-width and many grooves. Therefore, the driving electrode with smaller-width and many grooves was effective in low voltage and high speed operation.

• Korean Journal of Metals and Materials
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• v.48 no.7
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• pp.667-673
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• 2010

Copper filling into TSV (through-silicon-via) and reduction of the filling time for the three dimensional chip stacking were investigated in this study. A Si wafer with straight vias - $30\;{\mu}m$ in diameter and $60\;{\mu}m$ in depth with $200\;{\mu}m$ pitch - where the vias were drilled by DRIE (Deep Reactive Ion Etching) process, was prepared as a substrate. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to reduce the time required complete the Cu filling into the TSV, the PPR (periodic pulse reverse) wave current was applied to the cathode of a Si chip during electroplating, and the PR (pulse-reverse) wave current was also applied for a comparison. The experimental results showed 100% filling rate into the TSV in one hour was achieved by the PPR electroplating process. At the interface between the Cu filling and Ti/ Au functional layers, no defect, such as a void, was found. Meanwhile, the electroplating by the PR current showed maximum 43% filling ratio into the TSV in an hour. The applied PPR wave form was confirmed to be effective to fill the TSV in a short time.

• Korean Chemical Engineering Research
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• v.52 no.3
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• pp.382-387
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• 2014

The PC/ABS blends were manufactured with high shear rate processing. Changes of the blend morphology were analyzed according to the screw speed and processing time. To find optimal conditions of the high shear rate processing of the PC/ABS blend, blend morphology and size of the dispersed phase, ABS, were observed with a SEM. Also, tensile properties of the PC/ABS blends were measured to investigate the effect of the high shear rate process with the screw speed of 500 rpm to 3000 rpm for processing times of 10s to 40s. Especially, to observe the dispersed phase of the PC/ABS blend clearly, fracture surfaces of the PC/ABS blend were etched with chromic acid solution. As screw speed and processing time increase, dispersed phase size of the PC/ABS blend decreases and mechanical properties of the blend decrease as well. Especially, at screw speed over than 1000 rpm of high shear rate processing, mechanical properties of the PC/ABS blends decrease drastically due to the degradation of the blend during the high shear rate processing. Consequently, the optimal condition of screw speed of the high shear processing of the PC/ABS blend is set at 1000rpm, in this study. Under optimal condition, the PC/ABS blend has relatively high mechanical properties with the relatively stable micro-structure having nanometer scale dispersed phase.

• Korean Journal of Optics and Photonics
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• v.8 no.4
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• pp.327-332
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• 1997

We fabricated the high speed 1.55${\mu}{\textrm}{m}$ distributed feedback laser diodes (DFB-LD) using both two-step mesa etching process and semi-insulating InP current blocking layers. The devices characteristics were threshold current of ~15mA, slope efficiency of ~0.13mW/mA, and dynamic resistance of ~6.0Ω, with as-cleaved facets. The fabricated DFB-LD showed the single longitudinal mode with more than 40dB up to 6 $I_{th}$(CW condition), emitting at the wavelength of 0.546${\mu}{\textrm}{m}$. The -3dB bandwidth was >10㎓ at the driving current of 27mA, and the maximum -3dB bandwidth was ~18㎓ at 90 mA current, showing the superior frequency response of SI-PBH DFB-LD. In the 10Gb/s transmission experiment for 1.55${\mu}{\textrm}{m}$ DFB-LD module, maximum 10 km of single mode fiber(SMF) or 80 km of dispersion shifted fiber (DSF) could be transmitted with error free.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.21-28
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• 1999

A new method of making high speed self-aligned ESD (Elevated Source/Drain) MOSFET is proposed. Different from the conventional LDD (Lightly-Doped Drain) structure, the proposed ESD structure needs only one ion implantation step for the source/drain junctions, and makes it possible to modify the depth of the recessed channel by use of dry etching process. This structure alleviates hot-carrier stress by use of removable nitride sidewall spacers. Furthermore, the inverted sidewall spacers are used as a self-aligning mask to solve the self-align problem. Simulation results show that the impact ionization rate ($I_{SUB}/I_{D}$) is reduced and DIBL (Drain Induced Barrier Lowering) characteristics are improved by proper design of the structure parameters such as channel depth and sidewall spacer width. In addition, the use of removable nitride sidewall spacers also enhances hot-carrier characteristics by reducing the peak lateral electric field in the channel.

• Journal of the Korean Society for Heat Treatment
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• v.25 no.1
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• pp.6-13
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• 2012

HVOF thermal spray coating of 80%WC-CoFe powder is one of the most promising candidate for the replacement of the traditional hard chrome plating and hard ceramics coating because of the environmental problem of the very toxic $Cr^{6+}$ known as carcinogen by chrome plating and the brittleness of ceramics coatings. 80%WC-CoFe powder was coated by HVOF thermal spraying for the study of durability improvement of the high speed spindle such as air bearing spindle. The coating procedure was designed by the Taguchi program, including 4 parameters of hydrogen and oxygen flow rates, powder feed rate and spray distance. The surface properties of the 80%WC-CoFe powder coating were investigated roughness, hardness and porosity. The optimal condition for thermal spray has been ensured by the relationship between the spary parameters and the hardness of the coatings. The optimal coating process obtained by Taguchi program is the process of oxygen flow rate 34 FRM, hydrogen flow rate 57 FRM, powder feed rate 35 g/min and spray distance 8 inch. The coating cross-sectional structure was observed scanning electron microscope before chemical etching. Estimation of coating porosity was performed using metallugical image analysis. The Friction and wear behaviors of HVOF WC-CoFe coating prepared by OCP are investigated by reciprocating sliding wear test at $25^{\circ}C$ and $450^{\circ}C$. Friction coefficients (FC) of coating decreases as sliding surface temperature increases from $25^{\circ}C$ to $450^{\circ}C$.