• International Journal of Fuzzy Logic and Intelligent Systems
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• v.8 no.1
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• pp.75-81
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• 2008

This paper presents a top-down approach to implement an MPEG-2 audio encoder in VLSI. As the algorithm of an MPEG-2 audio encoder is heavy-weighted and heterogeneous(to be mixture of several strategies), the encoder design process is undertaken carefully from the algorithmic level to the architectural level. Firstly, the encoding algorithm is analyzed and divided into sub-algorithms, called tasks, and the tasks are partitioned in the way of reusing the same designs. Secondly, the partitioned tasks are scheduled and synthesized to make the most efficient use of time and space. In the end, a real-time 5 channel MPEG-2 audio encoder is designed which is a heterogeneous multiprocessor system; two hardwired logic blocks and one specialized DSP processor.

• The KIPS Transactions:PartD
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• v.15D no.3
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• pp.355-360
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• 2008

The complicated embedded system for multi-tasking requires RTOS(real-time operating system). It uses the optimal OS and processor to each embedded system on the heterogeneous development environment. This paper is proposed to use UML profile of OS API and Processor Configuration, instead of cross-compiling for developing the heterogeneous embedded system. This reduces the development time and cost through generating the automatic source code with the profile information of each embedded system. We generate and port the code after modeling the two heterogeneous real time operating systems (brickOS and uC/OS-II) and the processors (Hitachi H8 and Intel PXA255) with our proposed profile of the heterogeneous embedded system.

• The KIPS Transactions:PartA
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• v.14A no.7
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• pp.451-456
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• 2007

In this paper, we regard computer systems as heterogeneous multi-server systems and propose a cumulative fair scheduling scheme that pursues long-term fairness. GPS(generalized processor sharing)-based scheduling algorithms, which are usually employed in single-server systems, distribute available capacity in an instantaneous manner. However, applying them to heterogeneous multi-server systems may cause unfairness, since they may not prevent the accumulation of scheduling delays and the extra capacities are distributed in an instantaneous manner. In our scheme, long-term fairness is pursued by proper distribution of extra capacities while guaranteeing reserved capacities. A reference capacity model to determine the ideal progresses of applications is derived from long-term observations, and the scheduler makes the applications gradually follow the ideal progresses while guaranteeing their reserved capacities. A heuristic scheduling algorithm is proposed and the scheme is examined by simulation.

• Journal of Advanced Navigation Technology
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• v.14 no.1
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• pp.57-65
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• 2010

In this paper, we propose the structure of heterogeneous multiprocessor's concept, which is the structure of the new type of the robot controller, and we introduce an integrating structure method, which is distributed multiprocessor within controller using sRIO. We also perform the computer simulation with using the sRIO IP core which was designed within FPGA as the method for implementation of integrated heterogeneous multiprocessor by sRIO communication. Thus, we verify the result.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2007.04a
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• pp.327-332
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• 2007

An engineering design problem involving Multi-Disciplinary Analysis(MDA) generally requires a large amounts of CPU time for the entire design process, and therefore Multiple Processing System (MPS) are essential to reduce the completion time. However, when applying conventional parallel processing techniques, all of the CAE S/W required for the MDA should be installed on all the servers making up NIPS because of characteristic of MDA and it would be a great expense in CAE S/W licenses. To solve this problem, we propose a Weight-based Multiqueue Load Balancing algorithm for a heterogeneous MPS where performance of servers and CAE S/W installed on each server are different of each other. To validate the performance, a computational experiments comparing the First Come First Serve algorithm and our proposed algorithm was accomplished.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.11-19
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• 2015

Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

• The Transactions of the Korea Information Processing Society
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• v.5 no.5
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• pp.1151-1161
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• 1998

In this paper, we are considering a heterogeneous processor system in which each processor may have different performance and reliability characteristics. In other to fully utilize this diversity of processing power it is advantageous to assign the program modules of a distributed program to the processors in such a way that the execution time of the entire program is minimized. This assignment of tasks to processors to maximize performance is commonly called load balancing, since the overloaded processors can perform their own processing with the performance degradation. For the task assignment problem, we propose a new objective function which formulates this imbalancing cost. Thus the task assignment problem is to be carried out so that each module is assigned to a processor whose capabilities are most appropriate for the module, and the total cost is minimized that sum of inter-processor communication cost and execution cost and imbalance cost of the assignment. To find optimal assignment is known to be NP-hard, and thus we proposed an efficient heuristic algorithm with time complexity $O(n^2m)$ in case of m task modules and n processors.

• Journal of KIISE:Software and Applications
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• v.34 no.8
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• pp.697-707
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• 2007

Since embedded software is very dependent for target hardware architecture, characteristics of the platform must be considered when designing the software. Furthermore, MPSoCs consists of heterogeneous hardware components that are specified in micro level. Thus mapping of embedded software for MPSoCs should be considered the characteristics. In this paper, we provide an approach to automatic mapping PIM (Platform Independent Model) of an embedded software to PSM(Platform Specific Model) for MPSoC(Multi Processor System On Chip) and verify its effectiveness with simulation. In the proposed approach, tasks are derived from an object oriented model based on the UML (Unified Modeling Language). And then the types of the derived tasks are identified. With the identified types and inter relationship between tasks, the tasks are assigned to appropriate heterogeneous hardware components. We expect that the approach improve accuracy of the assigning and concurrency of the deployed software.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.20 no.3
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• pp.281-286
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• 2007

An engineering design problem involving Multi-Disciplinary Analysis(MDA) generally requires a large amounts of computing time for the entire design process, and therefore it is essential to introduce a Multiple Processor System (MPS) for reducing the computing time. However, when applying conventional parallel processing techniques, all of the CAE S/W requited for the MDA should be installed on all the servers making up MPS because of characteristic of MDA and it would be a great expense in CAE S/W licenses. To solve this problem, we propose a Weight-based Multiqueue Load Balancing algorithm for a heterogeneous MPS where performance of servers and CAE S/W installed on each server are different of each other. To validate the performance, a Computational experiments comparing the First Come First Serve algorithm and our proposed algorithm was accomplished.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.40-49
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• 2011

Integrating massive components and low-power policies have been actively investigated for system-on-chip designs. But in recent years, finding the optimal interconnection structure among heterogeneous components has emerged as a critical system design issue. Therefore, various simulation tools to model interconnection designs are being developed and performance evaluation of simulation is reflected in the real design. But most of the simulation environments employ traffic generation based on the mathematical probability functions, and such traffic generation cannot fully cover for various situations that may be occurred in the real system. Therefore, the demand for traffic pattern generation based on real applications is increasing. However, there have been few simulators that adopt application-specific traffic generators. This paper proposes a novel traffic generation method in simulating various interconnection structures for multi-processor system-on-chip design. The proposed traffic generation method can generate traffic patterns that can reflect the actual characteristics of the application and evaluate the performance of an interconnection structure under more realistic circumstance than traffic patterns using mathematical probability functions. By comparing the differences between the proposed method and the one based on mathematical probability functions, this paper shows advantages of the proposed traffic generation method.