• 제목/요약/키워드: hetero epitaxy

검색결과 15건 처리시간 0.018초

광소자로 사용되는 ZnTe박박의 결정성에 따른 결함 관찰 (Crystallinity and Internal Defect Observation of the ZnTe Thin Film Used by Opto-Electronic Sensor Material)

  • Kim, B.J.
    • 한국표면공학회지
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    • 제35권5호
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    • pp.289-294
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    • 2002
  • ZnTe films have been grown on (100) GaAs substrate with two representative problems. The one is lattice mismatch, the other is thermal expansion coefficients mismatch of ZnTe /GaAs. It claims here, the relationship of film thickness and defects distribution with (100) ZnTe/GaAs using hot wall epitaxy (HWE) growth was investigated by transmission electron microscopy (TEM). It analyzed on the two-sort side using TEM with cross-sectional transmission electron microscopy (XTEM) and high-resolution electron microscopy (HREM). Investigation into the nature and behavior of dislocations with dependence-thickness in (100) ZnTe/ (100) GaAs hetero-structures grown by transmission electron microscopy (TEM). This defects range from interface to 0.7 $\mu\textrm{m}$ was high density, due to the large lattice mismatch and thermal expansion coefficients. The defects of low density was range 0.7$\mu\textrm{m}$~1.8$\mu\textrm{m}$. In the thicker range than 1.8$\mu\textrm{m}$ was measured hardly defects.

Complementary FET로 열어가는 반도체 미래 기술 (Complementary FET-The Future of the Semiconductor Transistor)

  • 김상훈;이성현;이왕주;박정우;서동우
    • 전자통신동향분석
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    • 제38권6호
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    • pp.52-61
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    • 2023
  • With semiconductor scaling approaching the physical limits, devices including CMOS (complementary metal-oxide-semiconductor) components have managed to overcome yet are currently struggling with several technical issues like short-channel effects. Evolving from the process node of 22 nm with FinFET (fin field effect transistor), state-of-the-art semiconductor technology has reached the 3 nm node with the GAA-FET (gate-all-around FET), which appropriately addresses the main issues of power, performance, and cost. Technical problems remain regarding the foundry of GAA-FET, and next-generation devices called post-GAA transistors have not yet been devised, except for the CFET (complementary FET). We introduce a CFET that spatially stacks p- and n-channel FETs on the same footprint and describe its structure and fabrication. Technical details like stacking of nanosheets, special spacers, hetero-epitaxy, and selective recess are more thoroughly reviewed than in similar articles on CFET fabrication.

표면 광전압을 이용한 ZnSe 에피층의 특성 연구 (A study on characteristics of ZnSe epilayer by using surface photovoltage)

  • 최상수;정명랑;김주현;배인호;박성배
    • 한국진공학회지
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    • 제10권3호
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    • pp.350-355
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    • 2001
  • 반절연성 GaAs 위에 분자선 에피택시(MBE)법으로 성장된 ZnSe 에피층의 특성을 표면 광전압(SPV)법을 이용하여 연구하였다. 측정으로는 증가하는 광세기 및 변조 주파수에 따라 시행하였다. 미분한 표면 광전압(DSPV) 신호로부터 ZnSe 에피층의 띠간 에너지는 결정되었다. 실온의 표면 광전압 신호로부터 5개의 준위들이 관측되었는데, 이러한 준위들은 성장시 계면에서 형성되는 불순물 및 결함과 관계된다. 관측된 준위들은 입사광 세기에 따른 외인성 전이의 경향을 보여주었다. 실온에서 관측되지 않은 1s와 2s 엑시톤 흡수와 관계된 신호가 80 K에서 측정한 표면 광전압 스펙트럼에서 두 개의 피크로 분리되어 나타났다. 변조 주파수 의존성으로부터 시료의 접합콘덕턴스 및 용량을 구하였다.

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SiGe HBT의 Current Gain특성 향상 (Current Gain Enhancement in SiGe HBTs)

  • 송오성;이상돈;김득중
    • 한국산학기술학회논문지
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    • 제5권4호
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    • pp.367-370
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    • 2004
  • 초고속 RF IC의 핵심소자인 SiGe 에피텍시층을 가진 이종양극트란지스터(hetero junction bipolar transistor: HBT)를 0.35㎛급 Si-Ge BiCMOS공정으로 제작하였다. 낮은 VBE영역에서의 current gain의 선형성을 향상시키기 위하여 SiGe에피텍시층의 결함밀도를 감소시킬 수 있는 캐핑실리콘의 두께와 EDR온도의 최적화 공정조건을 알아보았다. 캐핑 실리콘의 두께를 200Å과 300Å으로 나누고 초고속 무선통신에서 요구되는 낮은 노이즈를 위한 EDR(Emitter Drive-in RTA)의 온도와 시간을 900-1000℃, 0-30 sec로 각각 변화시키면서 최적조건을 확인하였다. 실험범위 내에서의 최적공정조건은 300Å의 capping 실리콘과 975℃-30sec의 EDR 조건을 확인하였다.

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A Brief Study on the Fabrication of III-V/Si Based Tandem Solar Cells

  • Panchanan, Swagata;Dutta, Subhajit;Mallem, Kumar;Sanyal, Simpy;Park, Jinjoo;Ju, Minkyu;Cho, Young Hyun;Cho, Eun-Chel;Yi, Junsin
    • Current Photovoltaic Research
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    • 제6권4호
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    • pp.109-118
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    • 2018
  • Silicon (Si) solar cells are the most successful technology which are ruling the present photovoltaic (PV) market. In that essence, multijunction (MJ) solar cells provided a new path to improve the state-of-art efficiencies. There are so many hurdles to grow the MJ III-V materials on Si substrate as Si with other materials often demands similar qualities, so it is needed to realize the prospective of Si tandem solar cells. However, Si tandem solar cells with MJ III-V materials have shown the maximum efficiency of 30 %. This work reviews the development of the III-V/Si solar cells with the synopsis of various growth mechanisms i.e hetero-epitaxy, wafer bonding and mechanical stacking of III-V materials on Si substrate. Theoretical approaches to design efficient tandem cell with an analysis of state-of-art silicon solar cells, sensitivity, difficulties and their probable solutions are discussed in this work. An analytical model which yields the practical efficiency values to design the high efficiency III-V/Si solar cells is described briefly.