• Journal of the Korean institute of surface engineering
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• v.35 no.5
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• pp.289-294
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• 2002

ZnTe films have been grown on (100) GaAs substrate with two representative problems. The one is lattice mismatch, the other is thermal expansion coefficients mismatch of ZnTe /GaAs. It claims here, the relationship of film thickness and defects distribution with (100) ZnTe/GaAs using hot wall epitaxy (HWE) growth was investigated by transmission electron microscopy (TEM). It analyzed on the two-sort side using TEM with cross-sectional transmission electron microscopy (XTEM) and high-resolution electron microscopy (HREM). Investigation into the nature and behavior of dislocations with dependence-thickness in (100) ZnTe/ (100) GaAs hetero-structures grown by transmission electron microscopy (TEM). This defects range from interface to 0.7 $\mu\textrm{m}$ was high density, due to the large lattice mismatch and thermal expansion coefficients. The defects of low density was range 0.7$\mu\textrm{m}$~1.8$\mu\textrm{m}$. In the thicker range than 1.8$\mu\textrm{m}$ was measured hardly defects.

• Electronics and Telecommunications Trends
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• v.38 no.6
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• pp.52-61
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• 2023

With semiconductor scaling approaching the physical limits, devices including CMOS (complementary metal-oxide-semiconductor) components have managed to overcome yet are currently struggling with several technical issues like short-channel effects. Evolving from the process node of 22 nm with FinFET (fin field effect transistor), state-of-the-art semiconductor technology has reached the 3 nm node with the GAA-FET (gate-all-around FET), which appropriately addresses the main issues of power, performance, and cost. Technical problems remain regarding the foundry of GAA-FET, and next-generation devices called post-GAA transistors have not yet been devised, except for the CFET (complementary FET). We introduce a CFET that spatially stacks p- and n-channel FETs on the same footprint and describe its structure and fabrication. Technical details like stacking of nanosheets, special spacers, hetero-epitaxy, and selective recess are more thoroughly reviewed than in similar articles on CFET fabrication.

• Journal of the Korean Vacuum Society
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• v.10 no.3
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• pp.350-355
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• 2001

We have investigated characteristics of ZnSe epilayer grown by molecular beam epitaxy(MBE) on semi-insulating(SI) GaAs by using surface photovoltage(SPV). The measurements of SPV were performed with illumination intensity and modulation frequency. The bandgap energy of ZnSe epilayer was determined from derivative surface photovoltage (DSPV). The five states were observed at room temperature(RT), and those states relate to the impurity and defect formed hetero-interface of ZnSe and GaAs during the sample growth. The observed states represented as a tendency of typical extrinsic transition on the increasing illumination intensity. The 1s and 2s signals related to the excitonic absorption were not observed at RT, but those were presented with the splitted of two peaks in the SPV at 80 K. From the modulation frequency dependence, we obtained the junction conductance and capacitance of the sample.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.4
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• pp.367-370
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• 2004

We fabricated SiGe BiCMOS devices, which are important for ultra high speed RF IC chips, by employing $0.35\mu{m}$ CMOS process. To meet with the requirement of low noise level with linear base leakage current at low VBE region, we try to minimize polysilicon/ silicon interface traps by optimizing capping silicon thickness and EDR(emitter drive-in RTA) temperature. We employed $200\AA$and $300\AA$-thick capping silicon, and varied the EDR process condition at temperature of $900-1000^\circ{C}$, and time of 0-30 sec at a given capping silicon thickness. We investigated current gain behavior at each process condition. We suggest that optimum EDR process condition would be $975^\circ{C}$-30 sec with $300\AA$-thick capping silicon for proposed $0.35\mu{m}$-SiGe HBT devices.

• Current Photovoltaic Research
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• v.6 no.4
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• pp.109-118
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• 2018

Silicon (Si) solar cells are the most successful technology which are ruling the present photovoltaic (PV) market. In that essence, multijunction (MJ) solar cells provided a new path to improve the state-of-art efficiencies. There are so many hurdles to grow the MJ III-V materials on Si substrate as Si with other materials often demands similar qualities, so it is needed to realize the prospective of Si tandem solar cells. However, Si tandem solar cells with MJ III-V materials have shown the maximum efficiency of 30 %. This work reviews the development of the III-V/Si solar cells with the synopsis of various growth mechanisms i.e hetero-epitaxy, wafer bonding and mechanical stacking of III-V materials on Si substrate. Theoretical approaches to design efficient tandem cell with an analysis of state-of-art silicon solar cells, sensitivity, difficulties and their probable solutions are discussed in this work. An analytical model which yields the practical efficiency values to design the high efficiency III-V/Si solar cells is described briefly.