• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1996년도 Proceedings of the Korea Automatic Control Conference, 11th (KACC); Pohang, Korea; 24-26 Oct. 1996
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• pp.77-82
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• 1996

This paper is concerned with how to utilize kinematic redundancy to reconstruct the inverse kinematic solution which is not attainable due to hardware limitations. By analyzing the error due to hardware limitations, we are to show that the recoverability of limitation reduces to the solvability of a reconstruction equation under the feasibility condition. It will be next shown that the reconstruction equation is solvable if the configuration is not a joint-limit singularity. The reconstruction method will be proposed based on the geometrical analysis of recoverability of hardware limitations. The method has the feature that no task motion error is induced by the hardware limitations while minimizing a possible null motion error, under the recoverability assumed.

• 한국통신학회논문지
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• 제34권7B호
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• pp.744-750
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• 2009

본 논문에서는 신뢰성을 명가하는 데 있어서 소프트웨어 및 하드웨어 측면을 고려한 통합된 마코브 모델링(Markov modeling)으로 AVTMR(AlI Voting Triple Modular Redundancy) 시스템의 신뢰성을 분석한다. 본 시스템의 모델링은 하드웨어의 경우에 고장율이 시불변 특성을 가지며, 소프트웨어 경우에는 시 가변 특성으로 모델링되어 AVTMR 시스템과 단일 시스템에 대한 신뢰성 비교를 한다. 특히, 소프트웨어적인 특성은 G-O/NHPP 기법을 이용하여 분석이 되며, AVTMR 시스템의 전체적인 특성을 소프트웨어 및 하드웨어적인 관점에서 고장율 따른 특성을 이해할 수 있게 된다. 평가된 AVTMR 은 엄베디드 통신 시스템, 항공기 등의 결함 허용 시스댐에 요구되는 스팩에 맞도록 설계를 하기 위한 기반을 제시한다.

• 한국신뢰성학회지:신뢰성응용연구
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• 제1권1호
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• pp.9-15
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• 2001

This paper modelled the fail-safe control logic through the frequency coding input and designed the 3-out of-6 self checker using the error detect coding method of information redundancy. In addition, this paper also peformed the reliability parallel numeric analysis regarding single module between fail-safe. control logic module and TMR(Triple Modular Redundancy), therefore, we achieved the result that the fail-safe control logic increases a functional reliability because of decreasing system waste cost and functional overhead rather than the existing hardware redundancy method.

• Journal of Advanced Marine Engineering and Technology
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• 제28권8호
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• pp.1291-1298
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• 2004

In development of monitoring and control systems, one of the most important points is to consider a redundancy so that the system can be operated normally although hardware faults are partly occurred. The purpose of this paper is to introduce a monitoring and control system with a redundancy function for I/O servers and communication networks. I/O servers composed with an active server and a standby server. Each server also has 3 communication ports, 2 ports of them were connected to field units and the other 1 port was connected to the other server. Field units have to be constructed to 2 communication ports connected I/O servers through communication lines. Also, server communication module was implemented for analyzing and handling fault elements. and was submodularized for linking easily with a monitoring and control module. An experiment with 2 servers and 2 field units was constructed to demonstrate its effectiveness.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 B
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• pp.791-793
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• 1999

제어 컴퓨터의 고장으로 인해 인명이나 재산에 치명적 영향을 미치는 safety-critical 실시간 시스템을 제어하고 모니터링하기 위해 디지털 컴퓨터의 사용은 점점 일반화되고 있다. 특히, VLSI 기술의 급격한 발달로 인해 하드웨어가 초소형화 되고 대량생산이 가능해진 현실에서 이러한 제어 컴퓨터의 극대화된 신뢰도 요구를 만족시키기 위해 막중한 하드웨어 여분(hardware redundancy)이 널리 사용되고 있는 실정이다. 본 논문에서는 N개의 다중 모듈(multi-module)로 이루어진 하드웨어 여분의 운영 모드를 분석하고 각 운영 모드에서 고장이 발생할 경우 모드의 전환과 그로 인한 신뢰도의 변화를 계산할 것이다. 그리고 간단한 시뮬레이션을 통해 전환된 여러 모드 중 가장 우수한 신뢰도를 갖는 모드를 평가하게 된다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2014년도 추계학술대회 논문집
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• pp.11-12
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• 2014

This paper introduces a scaled hardware model for the 10kVA, 1kV, 11-level MMC (Modular Multilevel Converter), which was manufactured in the lab based on computer simulations with PSCAD/EMTDC. Various experiments were conducted to verify the major operation algorithms of MMC. The hardware scaled-model developed in the lab can be utilized for analyzing the operation analysis and performance evaluation of MMC according to the modulation pattern and redundancy operation scheme.

• 제어로봇시스템학회논문지
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• 제10권1호
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• pp.1-9
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• 2004

Inertial navigation system with hardware redundancy must use FDI(Fault Detection and Isolation) method to remove the influence of faulty sensors. Until now, several FDI methods such as PSA(Parity Space Approach), GLT(Generalized Likelihood ratio Test) and OPT(Optimal Parity vector Test) method are generally used. However, because these FDI methods only consider the situation that the system has one faulty sensor, these methods cannot be directly adapted for the system with two faulty sensors. To solve this problem, in this paper, PSA method is analyzed and based on this result, new FDI method called EPSA is proposed to consider a detection and an isolation of two faulty sensors in inertial navigation system.

• 대한전기학회논문지:시스템및제어부문D
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• 제50권4호
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• pp.168-176
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• 2001

In this paper, we develop a dual-duplex system which detects a fault by hardware comparator and switches to hot standby redundancy. This system is designed on the basis of MC68000 and can be used in VMEbus. To improve reliability, the dual-duplex system is designed in dual modular redundancy. The failure rate of electrical element is calculated in MILSPEC-217F, and the system RAMS(Reliability, Availiability, Maintainability and Safety) and MTTF(Mean Time to Failure) are evaluated by Markov modeling method. As the evaluation result shows improved reliability, it can be used as a component hardware for a highly reliable control system.

• 한국항공우주학회지
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• 제33권3호
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• pp.57-64
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• 2005

2자유도 관성센서는 두 입력축이 기계적으로 연관되어 있기 때문에 해당하는 관성센서의 두 입력축에 동시에 고장이 발생할 확률이 매우 높다. 따라서 하드웨어 여분만으로 고장검출 및 분리를 수행하기 위해서는 최소한 4개의 관성센서를 사용하여야 한다. 2자유도 관성센서를 3개 중첩해서 사용하는 경우 기존의 하드웨어 여분기법으로는 고장검출은 가능하나 고장분리가 불가능하다. 본 논문에서는 이러한 문제점을 개선하기 위해서 비선형 필터인 Unscented Kalman Filter를 이용하여 얻은 정보를 해석적 여분으로 활용하여, 하드웨어 여분과 해석적 여분을 동시에 고려한 복합 고장검출기법을 제안하였다. 제안한 복합 고장검출기법의 성능을 검증하기 위해서 비선형 항공기 수치 시뮬레이션을 수행하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.860-863
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• 2002

Realizations of multirate converters are proposed using periodically time-varying (PTV) structures. By exploiting the computational redundancy of the filtering operation in a multirate filter, it is possible to implement the filter with much less hardware. In the proposed implementations, several coefficients time-share in a periodic fashion the hardware of one multiply-and-add. Therefore, each multiply-and-add circuit performs different coefficient scalings at different time instants within a period. Compared to the direct form realization, the proposed realizations reduce the hardware of an interpolator and a decimator by a factor of approximately U and M, respectively, while retaining the same processing speed, where U and M are the upsampling and downsampling factors, respectively. The approach can be used to obtain realizations for sampling rate conversion by a rational factor of U/M, where U and M are relatively prime, in which case hardware reduction by a factor of approximately UM can be achieved.