• Journal of Information Processing Systems
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• v.5 no.4
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• pp.187-196
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• 2009

This paper presents compact cryptographic hardware architecture suitable for the Mobile Trusted Module (MTM) that requires low-area and low-power characteristics. The built-in cryptographic engine in the MTM is one of the most important circuit blocks and contributes to the performance of the whole platform because it is used as the key primitive supporting digital signature, platform integrity and command authentication. Unlike personal computers, mobile platforms have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore special architecture and design methods for a compact cryptographic hardware module are required. The proposed cryptographic hardware has a chip area of 38K gates for RSA and 12.4K gates for unified SHA-1 and SHA-256 respectively on a 0.25um CMOS process. The current consumption of the proposed cryptographic hardware consumes at most 3.96mA for RSA and 2.16mA for SHA computations under the 25MHz.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.2
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• pp.829-842
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• 2018

Unmanned Aerial Vehicle (UAV) is diversely utilized in our lives such as daily hobbies, specialized video image taking and disaster prevention activities. New ways of UAV application have been explored recently such as UAV-based delivery. However, most UAV systems are being utilized in a passive form such as real-time video image monitoring, filmed image ground analysis and storage. For more proactive UAV utilization, there should be higher-performance UAV and large-capacity memory than those presently utilized. Against this backdrop, this study described the general matters on proactive software platform and high-performance UAV hardware for real-time target tracking; implemented research on its design and implementation, and described its implementation method. Moreover, in its established platform, this study measured and analyzed the core-specific CPU consumption.

• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.6
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• pp.313-321
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• 2021

The global market for medical devices is huge, and it will continue showing remarkable growth in the future. However, due to the entry barrier to develop medical devices, many domestic companies have technical problems in entering the medical device industry. In this paper, we introduce an open platform that can help with research and development for companies in the healthcare industry. This open platform consists of a hardware part and a software part. A hardware part is combined into CPU, base and other modules that are easy to replace and assemble. A software part is based on application software for development developed by Bionet. We test the performance of the open medical device platform using a biosignal processing algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.12
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• pp.1688-1696
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• 2020

The paradigm of Internet-of-things(IoT) systems is changing from a cloud-based system to an edge-based system to solve delays caused by network congestion, server overload and security issues due to data transmission. However, edge-based IoT systems have fatal weaknesses such as lack of performance and flexibility due to various limitations. To improve performance, application-specific hardware can be implemented in the edge device, but performance cannot be improved except for specific applications due to a fixed function. This paper introduces a edge-centric metamorphic IoT(mIoT) platform that can use a variety of hardware through on-demand partial reconfiguration despite the limited hardware resources of the edge device, so we can increase the performance and flexibility of the edge device. According to the experimental results, the edge-centric mIoT platform that executes the reconfiguration algorithm at the edge was able to reduce the number of server accesses by up to 82.2% compared to previous studies in which the reconfiguration algorithm was executed on the server.

• Journal of the Institute of Convergence Signal Processing
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• v.13 no.2
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• pp.83-90
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• 2012

In this paper, an intelligent visual surveillance system based on a NIOS II embedded platform is implemented. By this time, embedded based visual surveillance systems were restricted for a special purpose because of high dependence upon hardware. In order to improve the restriction, we implement a flexible embedded platform, which is available for various purpose of applications. For high speed processing of software based programming, we improved performance of the system which is integrated the SOPC type of NIOS II embedded processor and image processing algorithms by using software programming and C2H(The Altera NIOS II C-To-Hardware(C2H) Acceleration Compiler) compiler in the core of the hardware platform. Then, we constructed a server system which globally manage some devices by the NIOS II embedded processor platform, and included the control function on networks to increase efficiency for user. We tested and evaluated our system at the designated region for visual surveillance.

• Journal of Korea Multimedia Society
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• v.19 no.4
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• pp.747-755
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• 2016

Automated guided vehicles have been used for a long time to increase work efficiency in the logistics field, but it is difficult to apply to a variety of logistics sites due to either the restricted movement mechanism or expensive devices. In this paper, we present a flexible software architecture that is hardware-independent for a mobile power cart of the follow mode and implement it using a ROS software platform. Through the SCV analysis for the system functionalities, we design a package to track a user movement and a package to control a new hardware platform. It has an advantage to use a variety of movement algorithms and hardware platforms by applying the strategy pattern and the template method pattern for the design of a software architecture. Through the performance evaluation, we show that the proposed design is maintainable in terms of a software complexity and it detects a user's movement by obtaining a user skeleton information so that it can control a hardware platform to move at a certain distance.

• Journal of information and communication convergence engineering
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• v.13 no.3
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• pp.145-151
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• 2015

We describe in this paper a hardware-based improvement scheme of a real-time automatic speech recognition (ASR) system with respect to speed by designing a parallel feature extraction algorithm on a Field-Programmable Gate Array (FPGA). A computationally intensive block in the algorithm is identified implemented in hardware logic on the FPGA. One such block is mel-frequency cepstrum coefficient (MFCC) algorithm used for feature extraction process. We demonstrate that the FPGA platform may perform efficient feature extraction computation in the speech recognition system as compared to the generalpurpose CPU including the ARM processor. The Xilinx Zynq-7000 System on Chip (SoC) platform is used for the MFCC implementation. From this implementation described in this paper, we confirmed that the FPGA platform is approximately 500× faster than a sequential CPU implementation and 60× faster than a sequential ARM implementation. We thus verified that a parallelized and optimized MFCC architecture on the FPGA platform may significantly improve the execution time of an ASR system, compared to the CPU and ARM platforms.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.1051-1059
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• 2008

In the development process of an ECU (Electrical Control Unit), numerous tests are necessary to evaluate the performance and control algorithm. The vehicle based test is expensive and requires long time. Also, it is difficult to guarantee the safety of the test driver. To overcome the various problems faced in the development process, the ECU test has been done using HIL (Hardware In the Loop). The HIL environment has the actual hardware including an ECU and a virtual vehicle model. In this paper, the test platform environment is devloped for the AWS ECU black box test. The test platform is built on HIL (Hardware In the Loop) architecture. Using the developed test platform, the control algorithm of the AWS ECU can be evaluated under the virtual driving condition of the bi-modal tram. Driving conditions, such as a front steering angle and vehicle velocity, are defined through the PC (Personal Computer) input. Input signals are transformed to electrical signals in the PC. These signals become the input conditions of the AWS ECU. The AWS ECU is stimulated by arbitory input conditons, and responses of the system are observed.

• Journal of Communications and Networks
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• v.13 no.1
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• pp.70-76
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• 2011

This paper presents the unified user equipment (UE) baseband modulation and demodulation (modem) hardware platform architecture to support multiple radio access technologies. In particular, this platform selectively supports two systems; one is HEDGE system, which is the combination of third generation partnership project (3GPP) Release 7 high speed packet access evolution (HSPA+) and global system for mobile communication (GSM)/general packet radio service (GPRS)/enhanced data rates for GSM evolution (EDGE), while the other is LEDGE system, which is the combination of 3GPP Release 8 long term evolution (LTE) and GSM/GPRS/EDGE. This is done by applying the flexible pin multiplexing scheme to a hardwired pin mapping process. On the other hand, to provide stable connection, high portability, and high debugging ability, the stacking structure is employed. Here, a layered board architecture grouped by functional classifications is applied instead of the conventional one flatten board. Based on this proposed configuration, we provide a framework for the verification step in wireless cellular communications. Also, modem function/scenario test and inter-operability test with various base station equipments are verified by system requirements and scenarios.

• Journal of IKEEE
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• v.17 no.2
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• pp.202-207
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• 2013

This paper implemented the conventional FAST and BRIEF algorithm as hardware on Zynq-7000 SoC Platform. Previous feature-based hardware accelerator is mostly implemented using the SIFT or SURF algorithm, but it requires excessive internal memory and hardware cost. The proposed FAST & BRIEF accelerator reduces approximately 57% of internal memory usage and 70% of hardware cost compared to the conventional SIFT or SURF accelerator, and it processes 0.17 pixel per Clock.