• Journal of IKEEE
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• v.23 no.4
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• pp.1400-1407
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• 2019

In this paper, we propose a support vector machine (SVM) based gas classifier that can support real-time self-learning. The modified sequential minimal optimization (MSMO) algorithm is employed to train the proposed SVM. By using a shared structure for learning and classification, the proposed SVM reduced the hardware area by 35% compared to the existing architecture. Our system was implemented with 3,337 CLB (configurable logic block) LUTs (look-up table) with Xilinx Zynq UltraScale+ FPGA (field programmable gate array) and verified that it can operate at the clock frequency of 108MHz.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.5 no.8
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• pp.1368-1387
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• 2011

In recent years, ubiquitous and pervasive scenarios have emerged as a complex ecosystem where differentiated software/hardware components interoperate wirelessly and seamlessly. The goal is to enable users to continuously access services and contents, and to always get the best out of their current environment and available resources. In such dynamic and flexible scenarios, the need emerges for flexible and general solutions for continuous runtime self-reconfiguration and self-optimization of ubiquitous support software systems. This paper proposes a fully reconfigurable middleware approach that aims at reconfiguring complex software systems made up of heterogeneous off-the-shelf components from both functional and non-functional perspectives. Our middleware can also extend already existing and non-reconfigurable middleware/applications in an easy and flexible way, with no need to re-design them. The proposed design principles have been practically applied to the implementation of a runtime self-reconfigurable middleware called Off-The-Shelf Ready To Go (OTS-RTG), implemented on top of iPOJO. The reported experimental results both exhibit a limited overhead and show the wide applicability of the proposed solution to many application scenarios, including complex, industrial, Enterprise Service Bus-based ones.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.9
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• pp.225-230
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• 2019

Recently, with the development of Internet technology, various encryption algorithms have been adopted to protect the sensing data measured by hardware devices. The Advanced Encryption Standard (AES), the most widely used encryption algorithm in the world, is also used in many devices with strong security. However, it has been found that the AES algorithm is vulnerable to side channel analysis attacks such as Differential Power Analysis (DPA) and Correlation Power Analysis (CPA). In this paper, we present a software optimization implementation technique of the AES algorithm applying the most widely known masking technique among side channel analysis attack methods.

• Journal of Magnetics
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• v.21 no.4
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• pp.544-553
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• 2016

Torque ripple minimization without decrease in average torque is a vital attribute in the design of Synchronous Reluctance (SynRel) motor. As the design of SynRel motor is an arduous task, which encompasses many design variables, this work first analyses the significance of the effect of varying the geometrical parameters on average torque and torque ripple and then proposes an extensive optimization procedure to obtain configurations with improved average torque and minimized torque ripple. A hardware prototype is fabricated and tested. The Finite Element Analysis (FEA) software tool used for validating the test results is MagNet 7.6.0.8. Multi Objective Particle Swarm Optimization (MOPSO) is used to determine the various designs meeting the requirements of reduced torque ripple and improved torque performance. The results indicate the efficacy of the proposed methodology and substantiate the utilization of MOPSO as a significant tool for solving design problems related to SynRel motor.

• The Journal of the Korea Contents Association
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• v.7 no.8
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• pp.59-65
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• 2007

Overlay Multicast is an effective method for efficient utilization of system resources and network bandwidth without a need for hardware customization. Multicast tree reconstruction is required when a non-leaf node leaves or fails. However frequent multicast tree reconstruction introduces serious degradation in performance. In this paper, we propose a tree performance optimization algorithm to solve this defect by using information(RTCP-probing) that becomes a periodic feedback to a source node from each child node. The proposed model is a mechanism performed when a parent node seems to cause deterioration in the tree performance. We have improved the performance of the whole service tree using the mechanism and hence composing an optimization tree. The simulation results show that our proposal stands to be an effective method that can be applied to not only the proposed model but also to existing techniques.

• The Journal of the Acoustical Society of Korea
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• v.19 no.4
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• pp.37-44
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• 2000

In this paper, we described the real-time implementation effort of MPEG-4 audio HVXC (Harmonic Vector eXcitation Coding) algorithm for very low bitrates, which has target applications from mobile communications to Internet telephony, on current high performance floating point TMS320C6701 DSP. We adopted a hardware structure for real-time operation. In order for software optimization, we used C- and assembly-language level optimizations for time-critical functional codes. Utilizing the internal program memory of the DSP as the program cache, the internal data memory overlap technique and DMA functionality, we could get a goal of realtime operation of HVXC codec both at 2 kbit/s and at 4 kbit/s. For an encoder at 2 kbit/s, the optimization ratio to original code is about 96 %. Finally, we got the subjective quality of MOS 2.45 at 2 kbit/s from an informal quality test.

• Journal of Digital Convergence
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• v.15 no.9
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• pp.223-230
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• 2017

In the current wireless Internet environment, using a mobile device to quickly access a web site is closely related to measuring the performance of a website. When accessing a website, the user has a long time to access the website and has no access to the website.In this case, the performance of the web site should be improved by measuring and analyzing the performance of the connection delay due to a problem of the web site.Among the performance measurement factors of Web sites, Web page loading time is a very important factor for a successful service business in the situation where most of e-commerce business is being developed as a web-based service.An open source tool was analyzed to analyze the performance of the e-commerce web page to present problems, software optimization methods and hardware optimization methods. Applying two optimization methods to suit the environment will enable stable and e-commerce websites.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.6
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• pp.115-121
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• 2015

In this paper, we proposed an iterative data-flow optimal scheduling algorithm based on genetic algorithm for high-performance multiprocessor. The basic hardware model can be extended to include detailed features of the multiprocessor architecture. This is illustrated by implementing a hardware model that requires routing the data transfers over a communication network with a limited capacity. The scheduling method consists of three layers. In the top layer a genetic algorithm takes care of the optimization. It generates different permutations of operations, that are passed on to the middle layer. The global scheduling makes the main scheduling decisions based on a permutation of operations. Details of the hardware model are not considered in this layer. This is done in the bottom layer by the black-box scheduling. It completes the scheduling of an operation and ensures that the detailed hardware model is obeyed. Both scheduling method can insert cycles in the schedule to ensure that a valid schedule is always found quickly. In order to test the performance of the scheduling method, the results of benchmark of the five filters show that the scheduling method is able to find good quality schedules in reasonable time.

• ETRI Journal
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• v.27 no.5
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• pp.491-496
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• 2005

An application specific processor for an H.264 decoder with a configurable embedded processor is designed in this research. The motion compensation, inverse integer transform, inverse quantization, and entropy decoding algorithm of H.264 decoder software are optimized. We improved the performance of the processor with instruction-level hardware optimization, which is tailored to configurable embedded processor architecture. The optimized instructions for video processing can be used in other video compression standards such as MPEG 1, 2, and 4. A significant performance improvement is achieved with high flexibility. Experimental results show that we could achieve 300% performance for the H.264 baseline profile level 2 decoder.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.177-180
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• 2000

This paper proposes the optimized hardware architecture for a high performance image downscaler The proposed downscaler uses non-linear digital filters for horizontal and vertical scalings. In order to achieve the optimization, the filters are implemented with multiplexer-adder type scheme and all the filter coefficients are selected on the order of two's power. The performance of the scaler is also verified by comparing with a pixel drop downscaler. The proposed scaler is designed by using the VHDL and implemented by using the IDEC-C632 0.65$\mu\textrm{m}$ cell library.