• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1797-1801
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• 2004

In this paper we show the hardware testbed and software simulator of multi function array radar (MFAR). The hardware MFAR is simple and flexible hardware to implement various radar beamforming and detecting algorithms. To overcome the limitation of hardware MFAR, the software simulator is proposed. User can simulate radar under the various environment conditions adjusting the parameter of simulator. User can set environment of radar, such as the location and velocity of target, jammer and the terrain clutter. The radar use various probing pulses and supports two operation mode, surveillance and tracking mode.

• Electronics and Telecommunications Trends
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• v.38 no.5
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• pp.81-89
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• 2023

Software is becoming increasingly important, accounting for more than 90% of the innovations in the automotive industry nowadays. In fact, the share of software in the automotive market is estimated to be around 40%. Accordingly, the shift from hardware- to software-centric vehicles, represented by software-defined vehicles (SDVs), will drastically reorganize the automotive industry ecosystem. This article presents challenges that the automotive ecosystem needs to solve and measures that each participant in the ecosystem should adopt in line with the transition to SDVs in the automotive industry. It is expected that tier-1 suppliers will face difficulties due to the decoupling of software and hardware, and OEMs will need to strengthen cooperation to share costs and shorten development periods to cope with the huge cost of software development.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.4
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• pp.448-456
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• 2000

As the system complexity increases, it is important to develop high-level verification techniques for fast and efficient design verifications. In this research, fast verification techniques for hardware and software co-design systems have been developed by using logic emulation and algorithm-level simulation. For faster and superior functional verification, we partition the system being designed into hardware and software parts, and implement the divided parts by using interface modules. We also propose several hardware design techniques for efficient hardware emulation. Experimental results, obtained by using a Reed-Solomon decoder system, show that our new verification methodology is more than 12,000 times faster than a commercial simulation tool for the modified Euclid's algorithm block and the overall verification time is reduced by more than 50%.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.40 no.3
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• pp.27-37
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• 2017

As the global uncertainty of manufacturing has increased and the quality problem has become global, the recall has become a fatal risk that determines the durability of the company. In addition, as the convergence of PSS (product-service system) product becomes common due to the development of IT convergence technology, if the function of any part of hardware or software does not operate normally, there will be a problem in the entire function of PSS product. In order to manage the quality of such PSS products in a stable manner, a new approaches is needed to analyze and manage the hardware and software parts at the same time. However, the Fishbone diagram, FTA, and FMEA, which are widely used to interpret the current quality problem, are not suitable for analyzing the quality problem by considering the hardware and software at the same time. In this paper, a quality risk assessment model combining FTA and FMEA based on defect rate to be assessed daily on site to manage quality and fishbone diagram used in group activity to solve defective problem. The proposed FTA-FMEA based risk assessment model considers the system structure characteristics of the defect factors in terms of the relationship between hardware and software, and further recognizes and manages them as risk. In order to evaluate the proposed model, we applied the functions of ITS (intelligent transportation system). It is expected that the proposed model will be more effective in assessing quality risks of PSS products because it evaluates the structural characteristics of products and causes of defects considering hardware and software together.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.321-326
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• 1992

In this paper, a high performance graphics system is suggested and its hardware architecture and software structure are described. The developed graphics system is a multi-processing system that uses 6 i860 RISC CPU's and supports PHIGS language in a hardware level. The software is programmed with respect to the graphics pipeline and the software modules are distributed into each processor for the optimization of the performance. The implemented graphics system can draw about 100,000 3D polygons second.

• Journal of Korea Multimedia Society
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• v.10 no.11
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• pp.1446-1459
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• 2007

This paper presents and analyzes a novel technique that makes it possible to improve the performance of low-end embedded systems through SoC(System-on-a-Chip) platform supporting dynamic cooperation between hardware and software modules. Traditional embedded systems with limited hardware resources have the poor capability of carrying out multi-tasking jobs including complex calculations. The proposed SoC platform, which provides dynamic cooperation between hardware and software modules, decomposes a single specific system into tasks for given system requirements. Additionally, we also propose a technique for efficient communication and synchronization between hardware and software tasks in cooperation with each other. Several experiments are conducted to illustrate the application and efficiency of the proposed SoC platform. They show that the proposed SoC platform outperforms the traditional embedded system, where only software tasks run, as the number of memory access is increased and the system become more complex.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.6
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• pp.547-558
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• 2008

Embedded system is tightly coupled with heterogeneous layers such as application, as kernel, device driver, HAL and hardware. Embedded system is customized for the specific purpose and hardware. In addition, the product cycle is so fast that software and hardware, which are developed by several vendors, are integrated together under unstable status. Therefore, there are lots of possibilities of faults in all layers. Because embedded software developers test their codes integrated with faulty layers, they cannot confirm 'whether testing of every aspects was completed, their code was failed, or integrated software/hardware has some problems'. In this paper, we propose an embedded software interface test method and a test tool called Justitia for detecting faults and tracing causes in the interface among heterogeneous layers. The proposed technique is an automated method which improves debugging upto professional testing using an emulator for helping developer.

• The Transactions of the Korea Information Processing Society
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• v.7 no.10
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• pp.3247-3261
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• 2000

In recent years, as the complexity of signal processmg systems Increases, the needs for dcslgners to mlx up hardware-part and software-part grow more and more considering both performance and cost There exist many algorilhms In C for vanous Signal processung apphcations. We have to translate the algonlhm C to hardware descnptlon language(HDL), If portion or the algonlhm needs to be unplcmenled in hardwarc pari of the syslcm. For this translation. it's dtfftcult to handle dynamic memory allocalion, function calls, pointer manipoJalion. This research shows a design method for a hardware model about recursive calls which was classified into software part of the system previously [or the translation from C to VHDL. The benefits of havlIlg recursive calls m hardware structure can be quite high since provides flexbility in hardware/software partitioming in codesign sysem.

• Journal of Advanced Navigation Technology
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• v.15 no.2
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• pp.298-306
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• 2011

In this paper, the RUNCODE encoder hardware IP was designed and implemented for symbol ID code length encoding, which is one of major modules of JBIG2 encoder for FAX. ImpulseC Codeveloper and Xilinx ISE/EDK program are used for the hardware generation and synthesis of VHDL code. The synthesized hardware was downloaded to Virtex-4 FX60 FPGA on ML410 development board. The synthesized hardware utilizes 13% of total slice of FPGA. Using Active-HDL tool, the hardware was verified showing normal operation. Compared with the software operating using Microblaze cpu on ML410 board, the synthesized hardware was better in operation time. The improvement ratio of operation time between the synthesized hardware and software showed about 40 times faster than software only operation. The synthesized H/W and S/W module cooperated to succeed in compressing the CCITT standard document.

• Journal of the Korea Society of Computer and Information
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• v.3 no.4
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• pp.70-77
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• 1998

The performance evaluation of system can be divided into software and hardware. Recently, many hardware evaluations have been developed as many fields, however, performance of software without any solution have been also developed. As a matter of cource, in a foreign country, software development tools and methodologies related to problems of performance engineering are suggested by paying much attentions on the software performance engineering. However in Korea, researches on those issues are wholly lacking. Therefore, in this paper, a software development methodology will be discussed and its contents will be compared as well.