• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.1
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• pp.9-26
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• 2005

In the pursuit of ever higher levels of performance, recent computer systems have made use of deep pipeline, dynamic scheduling and multi-issue superscalar processor technologies. In this situations, branch prediction schemes are an essential part of modem microarchitectures because the penalty for a branch misprediction increases as pipelines deepen and the number of instructions issued per cycle increases. In this paper, we propose a novel branch prediction scheme, direction-gshare(d-gshare), to improve the prediction accuracy. At first, we model a neural network with the components that possibly affect the branch prediction accuracy, and analyze the variation of their weights based on the neural network information. Then, we newly add the component that has a high weight value to an original gshare scheme. We simulate our branch prediction scheme using Simple Scalar, a powerful event-driven simulator, and analyze the simulation results. Our results show that, compared to bimodal, two-level adaptive and gshare predictor, direction-gshare predictor(d-gshare. 3) outperforms, without additional hardware costs, by up to 4.1% and 1.5% in average for the default mont of embedded direction, and 11.8% in maximum and 3.7% in average for the optimal one.

• Journal of the Korea Society of Computer and Information
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• v.13 no.4
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• pp.19-30
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• 2008

Branch history is one of major input vectors in branch prediction. Therefore, the Proper use of branch history plays a critical role of improving branch prediction accuracy. To improve branch prediction accuracy, this paper proposes a new branch history management policy, based on interrelationship analysis of instructions. First of all, we propose three different algorithms to analyze the relationship: register-writhing method, branch-reading method, and merged method. Then we additionally propose variable input gshare predictor as an implementation of these algorithms. In simulation part, we provide performance differences among the algorithms and analyze their characteristics. In addition, we compare branch prediction accuracy between our proposals and conventional fixed input predictors. The performance comparison for optimal input branch predictor is also provided.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.12
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• pp.1734-1737
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• 2019

This paper presents a prediction structure with a Hybrid Dynamic Branch Prediction (HDBP) scheme which decreases the number of stalls. In the application, a branch history register is dynamically adjusted to produce more unique index values of pattern history table (PHT). The number of stalls is also reduced by using the modified gshare predictor with a long history register folding scheme. The aliasing rate decreased to 44.1% and the miss prediction rate decreased to 19.06% on average compared with the gshare branch predictor, one of the most popular two-level branch predictors. Moreover, Compared with the gshare, an average improvement of 1.28% instructions per cycle (IPC) was achieved. Thus, with regard to the accuracy of branch prediction, the HDBP is remarkably useful in boosting the overall performance of the superscalar processor.

• Journal of Practical Agriculture & Fisheries Research
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• v.13 no.1
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• pp.3-17
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• 2011

Pipelines of processor have been growing deeper and issue widths wider over the years. If this trend continues, branch misprediction penalty will become very high. Branch misprediction is the single most significant performance limiter for improving processor performance using deeper pipelining. Therefore, more accurate branch predictor becomes an essential part of modem processors for FAFF(Food, Agriculture, Forestry, Fisheries)Information Processing. In this paper, we propose a branch prediction mechanism, using variable length history, which predicts using a bank having higher prediction accuracy among predictions from five banks. Bank 0 is a bimodal predictor which is indexed with the 12 least significant bits of the branch PC. Banks 1,2,3 and 4 are predictors which are indexed with different global history bits and the branch PC. In simulation results, the proposed mechanism outperforms gshare predictors using fixed history length of 12 and 13, up to 6.34% in prediction accuracy. Furthermore, the proposed mechanism outperforms gshare predictors using best history lengths for benchmarks, up to 2.3% in prediction accuracy.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.6
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• pp.306-313
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• 2005

Conditional branch prediction is an important technique for improving processor performance. Branch mispredictions, however, waste a large number of cycles, inhibit out-of-order execution, and waste electric power on mis-speculated instructions. Hence, the branch predictor with higher accuracy is necessary for good processor performance. In global-history-based predictors like gshare and GAg, many mispredictions come from commit update of the history. Some works on this subject have discussed the need for speculative update of the history and recovery mechanisms for branch mispredictions. In this paper, we present a simple mechanism for recovering the branch history after a misprediction. The proposed mechanism adds an age_counter to the original predictor and doubles the size of the branch history register. The age_counter counts the number of outstanding branches and uses it to recover the branch history register. Simulation results on the Simplescalar 3.0/PISA tool set and the SPECINTgS benchmarks show that gshare and GAg with the proposed recovery mechanism improved the average prediction accuracy by 2.14$\%$ and 9.21$\%$, respectively and the average IPC by 8.75$\%$ and 18.08$\%$, respectively over the original predictor.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04a
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• pp.22-24
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• 2001

슈퍼스칼라 프로세서에서는 분기 명령의 결과 지연으로 명령의 공급이 중단되는 것을 방지하고 지속적인 파이프라인 처리를 위해서 분기의 결과를 미리 예측하여 명령을 폐치하고 있다. 본 논문에서는 심플스칼라 툴 셋을 사용하여 슈퍼스칼라 프로세서에서 사용되는 대표적인 동적 분기예측 방법 시뮬레이션 환경을 구축한다. 동적 분기예측 방법으로 분기 타겟버퍼(Branch Target Buffer, BTB) 상에서 분기명령의 자기 히스토리에 근거한 BTB 방식과 이전 분기명령의 히스토리와의 상관관계를 고려한 Gshare 분기예측기를 적용 구현한다. 심플스칼라 시뮬레이터에 SPEC95 벤치마크 프로그램을 실행시켜 디자인 파라미터 변화에 따른 분기 예측기의 예측정확도를 실험한다. 또한 BTB와 Gshare 분기예측기를 VHDL로 구현하고 Synopsys 툴을 이용하여 시뮬레이션 및 합성 과정을 거쳐 게이트 크기와 파워 소모량을 측정한다.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.808-810
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• 2005

조건 분기예측실패는 많은 사이클을 낭비시키며, 비순서적 실행을 방해하고, 잘못 예측된 명령어들을 수행하게 되므로 전력을 낭비한다. gshare와 GAg같은 전역 히스토리를 기반으로 하는 예측기에서는 히스토리의 명령어 완료시간 갱신(commit update)에 의해 많은 분기예측실패가 발생한다. 이를 위해 히스토리를 모험적으로 갱신하고, 분기예측실패 시 히스토리를 복구시키는 메커니즘에 관한 연구들이 제시되었다. 본 논문에서는 기존 분기예측기에 age_Counter를 추가하여 미해결 분기명령어 수를 저장하며, 이를 분기예측실패 후 분기 히스토리 레지스터를 복구하는데 사용하는 간단한 복구 메커니즘을 제안한다. SimpleScalar 3.0/PISA 툴셋과 SPECINT95 벤치마크 프로그램에서 시뮬레이션 한 결과, 제안된 복구 메커니즘은 GAg와 gshare 예측기에서 예측정확도는 각각 $9.21\%$와 $2.14\%$가 개선되었고, IPC는 $18.08\%$와 $8.75\%$ 개선되었다.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.1
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• pp.33-40
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• 2007

Processor pipelines have been growing deeper and issue widths wider over the years. If this trend continues, the branch misprediction penalty will become very high. Branch misprediction is the single most significant performance limiter for improving processor performance using deeper pipelining. Therefore, more accurate branch predictor becomes an essential part of modern processors. Several branch predictors combine a part of the branch address with a fixed amount of global branch history to make a prediction. These predictors cannot perform uniformly well across all programs because the best amount of branch history to be used depends on the program and branches in the program. Therefore, predictors that use a fixed history length are unable to perform up to their potential performance. In this paper, we propose a branch prediction mechanism, using variable length history, which predicts using a bank having higher prediction accuracy among predictions from five banks. Bank 0 is a bimodal predictor which is indexed with the 12 least significant bits of the branch address. Banks 1, 2, 3 and 4 are predictors which are indexed with different global history bits and the branch PC. In simulation results, the proposed mechanism outperforms gshare predictors using fixed history length of 12 and 13 , up to 6.34% in prediction accuracy. Furthermore, the proposed mechanism outperforms gshare predictors using best history lengths for benchmarks, up to 2.3% in prediction accuracy.

• Agribusiness and Information Management
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• v.1 no.2
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• pp.43-60
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• 2009

To improve the performance of wide-issue superscalar processors, it is essential to increase the width of instruction fetch and the issue rate. Removal of control hazard has been put forward as a significant new source of instruction-level parallelism for superscalar processors and the conditional branch prediction is an important technique for improving processor performance. Branch mispredictions, however, waste a large number of cycles, inhibit out-of-order execution, and waste electric power on mis-speculated instructions. Hence, the branch predictor with higher accuracy is necessary for good processor performance. In global-history-based predictors like gshare and GAg, many mispredictions come from commit update of the branch history. Some works on this subject have discussed the need for speculative update of the history and recovery mechanisms for branch mispredictions. In this paper, we present a new mechanism for recovering the branch history after a misprediction. The proposed mechanism adds an age_counter to the original predictor and doubles the size of the branch history register. The age_counter counts the number of outstanding branches and uses it to recover the branch history register. Simulation results on the SimpleScalar 3.0/PISA tool set and the SPECINT95 benchmarks show that gshare and GAg with the proposed recovery mechanism improved the average prediction accuracy by 2.14% and 9.21%, respectively and the average IPC by 8.75% and 18.08%, respectively over the original predictor.

• Journal of the Korea Society of Computer and Information
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• v.21 no.9
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• pp.1-9
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• 2016

Recent embedded processors employ set-associative L1 instruction cache to improve the performance. The energy consumption in the set-associative L1 instruction cache accounts for considerable portion in the embedded processor. When an instruction is required from the processor, all ways in the set-associative instruction cache are accessed in parallel. In this paper, we propose the technique to reduce the energy consumption in the set-associative L1 instruction cache effectively by accessing only one way. Gshare branch predictor is employed to predict the instruction flow and determine the way to fetch the instruction. When the branch prediction is untaken, next instruction in a sequential order can be fetched from the instruction cache by accessing only one way. According to our simulations with SPEC2006 benchmarks, the proposed technique requires negligible hardware overhead and shows 20% energy reduction on average in 4-way L1 instruction cache.