• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.1
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• pp.11-18
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• 2017

Finite field arithmetic has been extensively used in error correcting codes and cryptography. Low-complexity and high-speed designs for finite field arithmetic are needed to meet the demands of wider bandwidth, better security and higher portability for personal communication device. In particular, cryptosystems in GF($2^m$) usually require computing exponentiation, division, and multiplicative inverse, which are very costly operations. These operations can be performed by computing modular AB multiplications or modular $AB^2$ multiplications. To compute these time-consuming operations, using $AB^2$ multiplications is more efficient than AB multiplications. Thus, there are needs for an efficient $AB^2$ multiplier architecture. In this paper, we propose a low latency Montgomery $AB^2$ multiplier using redundant representation over GF($2^m$). The proposed $AB^2$ multiplier has less space and time complexities compared to related multipliers. As compared to the corresponding existing structures, the proposed $AB^2$ multiplier saves at least 18% area, 50% time, and 59% area-time (AT) complexity. Accordingly, it is well suited for VLSI implementation and can be easily applied as a basic component for computing complex operations over finite field, such as exponentiation, division, and multiplicative inverse.

• Membrane Journal
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• v.19 no.4
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• pp.268-276
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• 2009

In this study the basic data were settled down to establish theory of membrane module and apparatus for measuring suspended solid per particle size. The theory and technique were different with the conventional weight method and light scattering method. For this purpose silica, dextran, kaolin, and PEG (polyethylene glycol) suspended solutions were filtrated through glass fiber membranes GF/C and GF/A on membrane module for measuring TMP (Trans-membrane pressure) changes using digital pressure gages. And the related equation between modified solution concentration and TMP change slope was derived from the TMP change experiments, and then suspended solid concentration of samples could be expected by the equation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.1C
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• pp.140-148
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• 2008

Using the self duality of an optimal normal basis(ONB) of type II, we present a bit parallel and bit serial systolic arrays over GF($2^m$) which has a low hardware complexity and a low latency. We show that our multiplier has a latency m+1 and the basic cell of our circuit design needs 5 latches(flip-flops). Comparing with other arrays of the same kinds, we find that our array has significantly reduced latency and hardware complexity.

• Restorative Dentistry and Endodontics
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• v.23 no.1
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• pp.269-277
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• 1998

This in vitro study compared the microleakage of 4 lining conditions when used with Gallium alloy GF II and Valiant PhD. Class V cavity was prepared on both buccal and lingual surface of 80 extracted human premolar & molar teeth with one margin in enamel and another in dentin. Before restoration, prepared cavities were applied to no-liner, cavity varnish, Scotchbond multipurpose, and Superbond D-liner II plus according to manufacture's instructions. The restored teeth were stored in saline for 1 week, then thermocycled for 100 times, stained with 0.5% basic fuchsin dye for 1 day, sectioned, and observed using a light microscope. Following results were obtained. 1. The leakage value of Superbond-lined group showed significantly lower than that of nolined group on both margins of Valiant PhD(p<0.05). 2; There was no significant difference between the 4 lining conditions in Gallium alloy GF II (p>0.05). 3. When We make a comparison between Gallium alloy GF II and Valiant PhD under same lining conditions, the microleakage value of Gallium alloy GF II showed lower than that of Valiant PhD on occlusal & gingival margin(p<0.05) except for Superbond-lined group(p>0.05).

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.7
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• pp.743-751
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• 1999

공개키 암호 시스템에서 모듈러 지수 연산은 주된 연산으로, 이 연산은 내부적으로 모듈러 곱셈을 반복적으로 수행함으로써 계산된다. 본 논문에서는 GF(2m)상에서 수행할 수 있는 Montgomery 알고리즘을 분석하여 right-to-left 방식의 모듈러 지수 연산에서 공통으로 계산 가능한 부분을 이용하여 모듈러 제곱과 모듈러 곱셈을 동시에 수행하는 선형 시스톨릭 어레이를 설계한다. 본 논문에서 설계한 시스톨릭 어레이는 기존의 곱셈기보다 모듈러 지수 연산시 약 0.67배 처리속도 향상을 가진다. 그리고, VLSI 칩과 같은 하드웨어로 구현함으로써 IC 카드에 이용될 수 있다.Abstract One of the main operations for the public key cryptographic system is the modular exponentiation, it is computed by performing the repetitive modular multiplications. In this paper, we analyze Montgomery's algorithm and design a linear systolic array to perform modular multiplication and modular squaring simultaneously. It is done by using common-multiplicand modular multiplication in the right-to-left modular exponentiation over GF(2m). The systolic array presented in this paper improves about 0.67 times than existing multipliers for performing the modular exponentiation. It could be designed on VLSI hardware and used in IC cards.

• Korean Journal of Materials Research
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• v.28 no.11
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• pp.615-619
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• 2018

To produce carbon electrodes for use in perovskite solar cells, electrode samples are prepared by mixing various weight ratios of 35 nm nano carbon(NC) and $1{\mu}m$ graphite flakes(GF), GF/(NC+GF) = 0, 0.5, 0.7, and 1, in chlorobenzene(CB) solvent with a $ZrO_2$ binder. The carbon electrodes are fabricated as glass/FTO/carbon electrode devices for microstructure characterization using transmission electron microscopy, optical microscopy, and a field emission scanning electron microscopy. The electrical characterization is performed with a four-point probe and a multi tester. The microstructure characterization shows that an electrode with excellent attachment to the substrate and no surface cracks at weight ratios above 0.5. The electrical characterization results show that the sheet resistance is <$70{\Omega}/sq$ and the interface resistance is <$70{\Omega}$ at weight ratios of 0.5 and 0.7. Therefore, a carbon paste electrode with microstructure and electrical properties similar to those of commercial carbon electrodes is proposed with an appropriate mixing ratio of NC and GF containing a CB solvent and $ZrO_2$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.686-689
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• 2009

This paper describes a scalar multiplier for Elliptic curve cryptography. The scalar multiplier has 163-bits key size which supports the specifications of smart card standard. To reduce the computational complexity of scalar multiplication on finite field $GF(2^{163})$, the Non-Adjacent-Format (NAF) conversion algorithm based on complementary recoding is adopted. The scalar multiplier core synthesized with a $0.35-{\mu}m$ CMOS cell library has 32,768 gates and can operate up to 150-MHz@3.3-V. It can be used in hardware design of Elliptic curve cryptography processor for smart card security.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.1
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• pp.41-47
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• 2008

This paper presents a new digit level LSB-first multiplier for computing a modular multiplication and a modular squaring simultaneously over finite field GF($2^m$). To derive $L{\times}L$ digit level architecture when digit size is set to L, the previous algorithm is used and index transformation and merging the cell of the architecture are proposed. The proposed architecture can be utilized for the basic architecture for the crypto-processor and it is well suited to VLSI implementation because of its simplicity, regularity, and concurrency.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.3
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• pp.87-94
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• 2002

This study presents an MSB(Most Significant Bit) Int multiplier using cellular automata, along with a new MSB first multiplication algorithm over GF($2^m$). The proposed architecture has the advantage of high regularity and a reduced latency based on combining the characteristics of a PBCA(Periodic Boundary Cellular Automata) and with the property of irreducible AOP(All One Polynomial). The proposed multiplier can be used in the effectual hardware design of exponentiation architecture for public-key cryptosystem.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.9
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• pp.1786-1792
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• 2015

Random linear network coding (RLNC) is widely employed to enhance the reliability of wireless multicast. In RLNC encoding/decoding, Galois Filed (GF) arithmetic is typically used since all the operations can be performed with symbols of finite bits. Considering the architecture of commercial computers, the complexity of arithmetic operations is constant regardless of the dimension of GF m, if m is smaller than 32 and pre-calculated tables are used for multiplication/division. Based on this, we show that the complexity of RLNC inversely proportional to m. Considering additional overheads, i.e., the increase of header length and memory usage, we determine the practical value of m. We implement RLNC in a commercial computer and evaluate the codec throughput with respect to the type of the tables for multiplication/division and the number of original packets to encode with each other.