• Journal of the Chungcheong Mathematical Society
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• v.27 no.1
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• pp.9-16
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• 2014

Let $\mathbb{A}=\mathbb{F}_q[T]$ be a polynomial ring over $\mathbb{F}_q$. In this paper we determine an asymptotic mean value of quadratic Dirich-let L-functions L(s, ${\chi}_{{\gamma}D}$) at the central point s=$\frac{1}{2}$, where D runs over all monic square-free polynomials of even degree in $\mathbb{A}$ and ${\gamma}$ is a generator of $\mathbb{F}_q^*$.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.6 no.4
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• pp.3-10
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• 1995

In this paper, application of PTCM to 2FSK / 4PSK signals is studied. The generator polynomial of punctured trellis coded 2FSK / 4PSK, metric computation techniques, decoding complexity considerations are provided. Simulation results shows that PTCM of 2FSK / 4PSK archieves equal coding gain in com- parison to Padovani and Wolf's system with less decoding complexity.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.2793-2795
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• 2005

고장검출식별시스템의 성능을 좌우하는 가장 중요한 요소는 잔차발생알고리즘이다. 잔차발생기구는 측정된 입출력변수 정보에 근거하여 설계되며 고장의 검출 및 식별이 가능하도록 감결합(decoupling) 특성을 가져야 한다. 본 논문에서는 전달함수 접근 방법 중 최근 제안된 최소차 다항식 기저(minimal polynomial basis)를 이용한 잔차발생기구 설계기법을 소개하고, 이를 VTOL의 센서 및 구동장치고장 검출에 적용하여 그 성능을 검토하였다.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.863-866
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• 1999

In this paper, we designed a Viterbi decoder with constraint length K=7, code rate R=1/2, encoder generator polynomial (171, 133)$_{8}$. This decoder makes use of 3-bit soft decision. We designed the Viterbi decoder using VHDL. We employed conventional logic circuit instead of ROM for branch metric units(BMUs) to reduce the number of gates. We adopted fully parallel structures for add-compare-select units(ACSUs). The size of the designed decoder is about 200, 000 gates.s.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.34 no.12
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• pp.472-484
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• 1985

A design of robust voltage controller for high speed excitation of synchronous machine was carried out by pole assignment techniques. An affine map from characteristic polynomial coefficients to feedback parameters is formulated in order to place the system eigen values in the desired region. The feedback parameters determined from linearized model are tested on nonlinear model subjecting it to small disturbances and system faults to show the effectiveness of the controller designed by the proposed technique. The results obtained indicate that the controller presented improves the dynamic stability and system performances of conventionally controlled synchronous machine significantly.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1209-1217
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• 2008

In this paper, we present a new bit-parallel multiplier for performing the bit-parallel multiplication of two polynomials in the finite fields $GF(2^m)$. Prior to construct the multiplier circuits, we consist of the vector code generator(VCG) to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial after performing the parallel multiplication of a multiplicand polynomial with a irreducible polynomial. The basic cells of VCG have two AND gates and two XOR gates. Using these VCG, we can obtain the multiplication results performing the bit-parallel multiplication of two polynomials. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields $GF(2^4)$. Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper use the VCGs with the basic cells repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSI.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.12
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• pp.1205-1214
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• 2013

Recently spaceborne SAR systems are increasing image resolution and frequency. As a high quality image resolution, the wider bandwidth is required and a wideband signal generator with RF component is very complicated and RF impairments of device is increased. Therefore, it is very important to improve performance by reducing these errors. In this study, the transmission signal of the wideband signal generator is applied to the phase noise, IQ imbalance, ripple gain, nonlinear model of high power amplifier. And we define possible structures of wideband signal generator and measure the PSLR and ISLR for the performance assesment. Also, we extract error of the amplitude and phase from the waveform and use a quadratic polynomial curve fitting and examine the performance change due to nonlinear device. Finally, we apply a high power amplifier predistortion method for non-linear error compensation. And we confirm that distortion in the output of the amplifier by intermodulation component is decreased by 15 dB.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.2
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• pp.333-342
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• 2022

Cellular Automata (CA) is a discrete and abstract computational model that is being applied in various fields. Applicable as an excellent pseudo-random sequence generator, CA has recently developed into a basic element of cryptographic systems. Several studies on CA-based stream ciphers have been conducted and it has been observed that the encryption strength increases when the radius of a CA's neighbor is increased when appropriate CA rules are used. In this paper, among CAs that can be applied as a one-dimensional pseudo-random number sequence generator (PRNG), one-dimensional 5-neighbor CAs are classified according to the connection state of their neighbors, and the ignition relationship of the characteristic polynomial is obtained. Also this paper propose a synthesis algorithm for an asymmetric 1-D linear 5-neighbor MLCA in which the radius of the neighbor is increased by 2 using the one-dimensional 3-neighbor 90/150 CA state transition matrix.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.83-88
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• 2008

The QPP interleaver has been gaining attention since it provides contention-free interleaving functionality for high speed parallel turbo decoders. In this paper we first show that the quadratic term $f_2x^2%K$ of $f(x)=(f_1x+f_2x^2)%K$, the address generating function, is periodic. We then introduce a low-power address generator which utilizes this periodic characteristic. This generator follows the conventional method to generate the interleaving addresses and also to save the quadratic term values during the first half of the first period. The saved values are then reused for generating further interleaved addresses, resulting in reduced number of logical operations. Power consumption is reduced by 27.38% in the design with fixed-K and 5.54% in the design with unfixed-K on average for various values of K, when compared with the traditional designs.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.6
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• pp.257-266
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• 2015

There is no polynomial-time algorithm that can be obtain the optimal solution for economic load dispatch problem with non-convex fuel cost functions. Therefore, electrical field uses quadratic fuel cost function unavoidably. This paper proposes a valve-point optimization (VPO) algorithm for economic load dispatch problem with non-convex fuel cost functions. This algorithm sets the initial values to maximum powers $P_i{\leftarrow}P_i^{max}$ for each generator. It then reduces the generation power of generator i with an average power cost of $_{max}\bar{c}_i$ to a valve point power $P_{ik}$. The proposed algorithm has been found to perform better than the extant heuristic methods when applied to 13 and 40-generator benchmark data. This paper consequently proves that the optimal solution to economic load dispatch problem with non-convex fuel cost functions converges to the valve-point power of each generator.