• JSTS:Journal of Semiconductor Technology and Science
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• 제9권3호
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• pp.136-147
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• 2009

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non-overlapped gate-source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.

• 대한전자공학회논문지SD
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• 제45권10호
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• pp.15-22
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• 2008

기존의 MOSFET는 단채널 현상의 증가로 인하여 스케일링에 한계를 가지고 있다. Double-Gate MOSFET (DG-MOSFET)는 소자의 길이가 축소되면서 나타나는 단채널 현상을 효과적으로 제어하는 차세대 소자이다. DG-MOSFET으로 소자를 축소시키면 채널 길이가 10nm 이하에서 게이트 방향뿐만 아니라 소스와 드레인 방향에서도 양자 효과가 발생한다. 또한 게이트 길이가 매우 짧아지면 ballistic transport 현상이 발생한다. 따라서 본 연구에서는 2차원 양자 효과와 ballistic transport를 고려하여 DG-MOSFET의 특성을 분석하였다. 또한 단채널 효과를 줄이기 위해서 $t_{si}$와 underlap 그리고 lateral doping gradient를 이용하여 소자 구조를 최적화하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권4호
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• pp.265-275
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• 2010

In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권2호
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• pp.170-177
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• 2008

In the present work a methodology to minimize short channel effects (SCEs) by modulating the effective channel length is proposed to design 25 nm single and double gate-source/drain underlap MOSFETs. The analysis is based on the evaluation of the ratio of effective channel length to natural/ characteristic length. Our results show that for this ratio to be greater than 2, steeper source/drain doping gradients along with wider source/drain roll-off widths will be required for both devices. In order to enhance short channel immunity, the ratio of source/drain roll-off width to lateral straggle should be greater than 2 for a wide range of source/drain doping gradients.