• Title/Summary/Keyword: gate-leakage current

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Time Dependence of Charge Generation and Breakdown of Re-oxidized Nitrided Oxide (재산화 질화 산화막의 전하 생성과 항복에 대한 시간 의존성)

  • 이정석;이용재
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.2 no.3
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    • pp.431-437
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    • 1998
  • In this paper, we have investigated the electrical properties of ultra-thin nitrided oxide(NO) and re-oxidized nitrided oxide(ONO) films that are considered to be promising candidates for replacing conventional silicon dioxide film in ULSI level integration. Especially, we have studied a variation of I-V characteristics, gate voltage shift, and time-dependent dielectric breakdown(TDDB) of thin layer NO and ONO film depending on nitridation and reoxidation time, respectively, and measured a variation of leakage current and charge-to-breakdown(Q$\_bd$) of optimized NO and ONO film depending on ambient temperature, and then compared with the properties of conventional SIO$\_2$. From the results, we find that these NO and ONO thin films are strongly influenced by process time and the optimized ONO film shows superior dielectric characteristics, and (Q$\_bd$) performance over the NO film and SIO$\_2$, while maintaining a similar electric field dependence compared with NO layer.

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Study of Al Doping Effect on HfO2 Dielectric Thin Film Using PEALD (PEALD를 이용한 HfO2 유전박막의 Al 도핑 효과 연구)

  • Min Jung Oh;Ji Na Song;Seul Gi Kang;Bo Joong Kim;Chang-Bun Yoon
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.36 no.2
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    • pp.125-128
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    • 2023
  • Recently, as the process of the MOS device becomes more detailed, and the degree of integration thereof increases, many problems such as leakage current due to an increase in electron tunneling due to the thickness of SiO2 used as a gate oxide have occurred. In order to overcome the limitation of SiO2, many studies have been conducted on HfO2 that has a thermodynamic stability with silicon during processing, has a higher dielectric constant than SiO2, and has an appropriate band gap. In this study, HfO2, which is attracting attention in various fields, was doped with Al and the change in properties according to its concentration was studied. Al-doped HfO2 thin film was deposited using Plasma Enhanced Atomic Layer Deposition (PEALD), and the structural and electrical characteristics of the fabricated MIM device were evaluated. The results of this study are expected to make an essential cornerstone in the future field of next-generation semiconductor device materials.

저온 공정 온도에서 $Al_2O_3$ 게이트 절연물질을 사용한 InGaZnO thin film transistors

  • 우창호;안철현;김영이;조형균
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.06a
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    • pp.11-11
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    • 2010
  • Thin-film-transistors (TFTs) that can be deposited at low temperature have recently attracted lots of applications such as sensors, solar cell and displays, because of the great flexible electronics and transparent. Transparent and flexible transistors are being required that high mobility and large-area uniformity at low temperature [1]. But, unfortunately most of TFT structures are used to be $SiO_2$ as gate dielectric layer. The $SiO_2$ has disadvantaged that it is required to high driving voltage to achieve the same operating efficiency compared with other high-k materials and its thickness is thicker than high-k materials [2]. To solve this problem, we find lots of high-k materials as $HfO_2$, $ZrO_2$, $SiN_x$, $TiO_2$, $Al_2O_3$. Among the High-k materials, $Al_2O_3$ is one of the outstanding materials due to its properties are high dielectric constant ( ~9 ), relatively low leakage current, wide bandgap ( 8.7 eV ) and good device stability. For the realization of flexible displays, all processes should be performed at very low temperatures, but low temperature $Al_2O_3$ grown by sputtering showed deteriorated electrical performance. Further decrease in growth temperature induces a high density of charge traps in the gate oxide/channel. This study investigated the effect of growth temperatures of ALD grown $Al_2O_3$ layers on the TFT device performance. The ALD deposition showed high conformal and defect-free dielectric layers at low temperature compared with other deposition equipments [2]. After ITO was wet-chemically etched with HCl : $HNO_3$ = 3:1, $Al_2O_3$ layer was deposited by ALD at various growth temperatures or lift-off process. Amorphous InGaZnO channel layers were deposited by rf magnetron sputtering at a working pressure of 3 mTorr and $O_2$/Ar (1/29 sccm). The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. The TFT devices were heat-treated in a furnace at $300^{\circ}C$ and nitrogen atmosphere for 1 hour by rapid thermal treatment. The electrical properties of the oxide TFTs were measured using semiconductor parameter analyzer (4145B), and LCR meter.

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Low-Power $32bit\times32bit$ Multiplier Design for Deep Submicron Technologies beyond 130nm (130nm 이하의 초미세 공정을 위한 저전력 32비트$\times$32비트 곱셈기 설계)

  • Jang Yong-Ju;Lee Seong-Soo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.6 s.348
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    • pp.47-52
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    • 2006
  • This paper proposes a novel low-power $32bit\times32bit$ multiplier for deep submicron technologies beyond 130nm. As technology becomes small, static power due to leakage current significantly increases, and it becomes comparable to dynamic power. Recently, shutdown method based on MTCMOS is widely used to reduce both dynamic and static power. However, it suffers from severe power line noise when restoring whole large-size functional block. Therefore, the proposed multiplier mitigates this noise by shutting down and waking up sequentially along with pipeline stage. Fabricated chip measurement results in $0.35{\mu}m$ technology and gate-transition-level simulation results in 130nm and 90nm technologies show that it consumes $66{\mu}W,\;13{\mu}W,\;and\;6{\mu}W$ in idle mode, respectively, and it reduces power consumption to $0.04%\sim0.08%$ of active mode. As technology becomes small, power reduction efficiency degrades in the conventional clock gating scheme, but the proposed multiplier does not.

The electrical characteristics of flexible organic field effect transistors with flexible multi-stacked hybrid encapsulation

  • Seol, Yeong-Guk;Heo, Uk;Park, Ji-Su;Lee, Nae-Eung;Lee, Deok-Gyu;Kim, Yun-Je;An, Cheol-Hyeon;Jo, Hyeong-Gyun
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.08a
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    • pp.176-176
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    • 2010
  • One of the critical issues for applications of flexible organic thin film transistors (OTFTs) for flexible electronic systems is the electrical stabilities of the OTFT devices, including variation of the current on/off ratio (Ion/Ioff), leakage current, threshold voltage, and hysteresis under repetitive mechanical deformation. In particular, repetitive mechanical deformation accelerates the degradation of device performance at the ambient environment. In this work, electrical stability of the pentacene organic thin film transistors (OTFTs) employing multi-stack hybrid encapsulation layers was investigated under mechanical cyclic bending. Flexible bottom-gated pentacene-based OTFTs fabricated on flexible polyimide substrate with poly-4-vinyl phenol (PVP) dielectric as a gate dielectric were encapsulated by the plasma-deposited organic layer and atomic-layer-deposited inorganic layer. For cyclic bending experiment of flexible OTFTs, the devices were cyclically bent up to 105 times with 5mm bending radius. In the most of the devices after 105 times of bending cycles, the off-current of the OTFT with no encapsulation layers was quickly increased due to increases in the conductivity of the pentacene caused by doping effects from $O_2$ and $H_2O$ in the atmosphere, which leads to decrease in the Ion/Ioff and increase in the hysteresis. With encapsulation layers, however, the electrical stabilities of the OTFTs were improved significantly. In particular, the OTFTs with multi-stack hybrid encapsulation layer showed the best electrical stabilities up to the bending cycles of $10^5$ times compared to the devices with single organic encapsulation layer. Changes in electrical properties of cyclically bent OTFTs with encapsulation layers will be discussed in detail.

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Enhanced Device Performance of IZO-based oxide-TFTs with Co-sputtered $HfO_2-Al_2O_3$ Gate Dielectrics (Co-sputtered $HfO_2-Al_2O_3$을 게이트 절연막으로 적용한 IZO 기반 Oxide-TFT 소자의 성능 향상)

  • Son, Hee-Geon;Yang, Jung-Il;Cho, Dong-Kyu;Woo, Sang-Hyun;Lee, Dong-Hee;Yi, Moon-Suk
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.6
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    • pp.1-6
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    • 2011
  • A transparent oxide thin film transistors (Transparent Oxide-TFT) have been fabricated by RF magnetron sputtering at room temperature using amorphous indium zinc oxide (a-IZO) as both of active channel and source/drain, gate electrodes and co-sputtered $HfO_2-Al_2O_3$ (HfAIO) as gate dielectric. In spite of its high dielectric constant > 20), $HfO_2$ has some drawbacks including high leakage current and rough surface morphologies originated from small energy band gap (5.31eV) and microcrystalline structure. In this work, the incorporation of $Al_2O_3$ into $HfO_2$ was obtained by co-sputtering of $HfO_2$ and $Al_2O_3$ without any intentional substrate heating and its structural and electrical properties were investigated by x-ray diffraction (XRD), atomic force microscopy (AFM) and spectroscopic ellipsometer (SE) analyses. The XRD studies confirmed that the microcrystalline structures of $HfO_2$ were transformed to amorphous structures of HfAIO. By AFM analysis, HfAIO films (0.490nm) were considerably smoother than $HfO_2$ films (2.979nm) due to their amorphous structure. The energy band gap ($E_g$) deduced by spectroscopic ellipsometer was increased from 5.17eV ($HfO_2$) to 5.42eV (HfAIO). The electrical performances of TFTs which are made of well-controlled active/electrode IZO materials and co-sputtered HfAIO dielectric material, exhibited a field effect mobility of more than $10cm^2/V{\cdot}s$, a threshold voltage of ~2 V, an $I_{on/off}$ ratio of > $10^5$, and a max on-current of > 2 mA.

CMOS 소자 응용을 위한 Plasma doping과 Silicide 형성

  • Choe, Jang-Hun;Do, Seung-U;Seo, Yeong-Ho;Lee, Yong-Hyeon
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.02a
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    • pp.456-456
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    • 2010
  • CMOS 소자가 서브마이크론($0.1\;{\mu}m$) 이하로 스케일다운 되면서 단채널 효과(short channel effect), 게이트 산화막(gate oxide)의 누설전류(leakage current)의 증가와 높은 직렬저항(series resistance) 등의 문제가 발생한다. CMOS 소자의 구동전류(drive current)를 높이고, 단채널 효과를 줄이기 위한 가장 효율적인 방법은 소스 및 드레인의 얕은 접합(shallow junction) 형성과 직렬 저항을 줄이는 것이다. 플라즈마 도핑 방법은 플라즈마 밀도 컨트롤, 주입 바이어스 전압 조절 등을 통해 저 에너지 이온주입법보다 기판 손상 및 표면 결함의 생성을 억제하면서 고농도로 얕은 접합을 형성할 수 있다. 그리고 얕은 접합을 형성하기 위해 주입된 불순물의 활성화와 확산을 위해 후속 열처리 공정은 높은 온도에서 짧은 시간 열처리하여 불순물 물질의 활성화를 높여주면서 열처리로 인한 접합 깊이를 얕게 해야 한다. 그러나 접합의 깊이가 줄어듦에 따라서 소스 및 드레인의 표면 저항(sheet resistance)과 접촉저항(contact resistance)이 급격하게 증가하는 문제점이 있다. 이러한 표면저항과 접촉저항을 줄이기 위한 방안으로 실리사이드 박막(silicide thin film)을 형성하는 방법이 사용되고 있다. 본 논문에서는 (100) p-type 웨이퍼 He(90 %) 가스로 희석된 $PH_3$(10 %) 가스를 사용하여 플라즈마 도핑을 실시하였다. 10 mTorr의 압력에서 200 W RF 파워를 인가하여 플라즈마를 생성하였고 도핑은 바이어스 전압 -1 kV에서 60 초 동안 실시하였다. 얕은 접합을 형성하기 위한 불순물의 활성화는 ArF(193 nm) excimer laser를 통해 $460\;mJ/cm^2$의 에니지로 열처리를 실시하였다. 그리고 낮은 접촉비저항과 표면저항을 얻기 위해 metal sputter를 통해 TiN/Ti를 $800/400\;{\AA}$ 증착하고 metal RTP를 사용하여 실리사이드 형성 온도를 $650{\sim}800^{\circ}C$까지 60 초 동안 열처리를 실시하여 $TiSi_2$ 박막을 형성하였다. 그리고 $TiSi_2$의 두께를 측정하기 위해 TEM(Transmission Electron Microscopy)을 측정하였다. 화학적 결합상태를 분석하기 위해 XPS(X-ray photoelectronic)와 XRD(X-ray diffraction)를 측정하였다. 접촉비저항, 접촉저항과 표면저항을 분석하기 위해 TLM(Transfer Length Method) 패턴을 제작하여 I-V 특성을 측정하였다. TEM 측정결과 $TiSi_2$의 두께는 약 $580{\AA}$ 정도이고 morphology는 안정적이고 실리사이드 집괴 현상은 발견되지 않았다. XPS와 XRD 분석결과 실리사이드 형성 온도가 $700^{\circ}C$에서 C54 형태의 $TiSi_2$ 박막이 형성되었고 가장 낮은 접촉비저항과 접촉저항 값을 가진다.

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Plasma Polymerized Styrene for Gate Insulator Application to Pentacene-capacitor (유기박막트랜지스터 응용을 위해 플라즈마 중합된 Styrene 게이트 절연박막)

  • Hwang, M.H.;Son, Y.D.;Woo, I.S.;Basana, B.;Lim, J.S.;Shin, P.K.
    • Journal of the Korean Vacuum Society
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    • v.20 no.5
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    • pp.327-332
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    • 2011
  • Plasma polymerized styrene (ppS) thin films were prepared on ITO coated glass substrates for a MIM (metal-insulator-metal) structure with thermally evaporated Au thin film as metal contact. Also the ppS thin films were applied as organic insulator to a MIS (metal-insulatorsemiconductor) device with thermally evaporated pentacene thin film as organic semiconductor layer. After the I-V and C-V measurements with MIM and MIS structures, the ppS revealed relatively higher dielectric constant of k=3.7 than those of the conventional poly styrene and very low leakage current density of $1{\times}10^{-8}Acm^{-2}$ at electric field strength of $1MVcm^{-1}$. The MIS structure with the ppS dielectric layer showed negligible hysteresis in C-V characteristics. It would be therefore expected that the proposed ppS could be applied as a promising dielectric/insulator to organic thin film transistors, organic memory devices, and flexible organic electronic devices.

Temperature Dependence on Dry Etching of $ZrO_2$ Thin Films in $Cl_2/BCl_3$/Ar Inductively Coupled Plasma ($Cl_2/BCl_3$/Ar 유도 결합 플라즈마에서 온도에 따른 $ZrO_2$ 박막의 식각)

  • Yang, Xue;Kim, Dong-Pyo;Lee, Cheol-In;Um, Doo-Seung;Kim, Chang-Il
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.145-145
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    • 2008
  • High-k materials have been paid much more attention for their characteristics with high permittivity to reduce the leakage current through the scaled gate oxide. Among the high-k materials, $ZrO_2$ is one of the most attractive ones combing such favorable properties as a high dielectric constant (k= 20 ~ 25), wide band gap (5 ~ 7 eV) as well as a close thermal expansion coefficient with Si that results in good thermal stability of the $ZrO_2$/Si structure. During the etching process, plasma etching has been widely used to define fine-line patterns, selectively remove materials over topography, planarize surfaces, and trip photoresist. About the high-k materials etching, the relation between the etch characteristics of high-k dielectric materials and plasma properties is required to be studied more to match standard processing procedure with low damaged removal process. Among several etching techniques, we chose the inductively coupled plasma (ICP) for high-density plasma, easy control of ion energy and flux, low ownership and simple structure. And the $BCl_3$ was included in the gas due to the effective extraction of oxygen in the form of $BCl_xO_y$ compounds. During the etching process, the wafer surface temperature is an important parameter, until now, there is less study on temperature parameter. In this study, the etch mechanism of $ZrO_2$ thin film was investigated in function of $Cl_2$ addition to $BCl_3$/Ar gas mixture ratio, RF power and DC-bias power based on substrate temperature increased from $10^{\circ}C$ to $80^{\circ}C$. The variations of relative volume densities for the particles were measured with optical emission spectroscopy (OES). The surface imagination was measured by scanning emission spectroscope (SEM). The chemical state of film was investigated using energy dispersive X-ray (EDX).

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Characteristics of $Ta_{2}O_{5}$ Films by RF Reactive Sputtering (RF 반응성 스펏터링으로 제조한 $Ta_{2}O_{5}$ 막의 특성)

  • Park, Wug-Dong;Keum, Dong-Yeal;Kim, Ki-Wan;Choi, Kyu-Man
    • Journal of Sensor Science and Technology
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    • v.1 no.2
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    • pp.173-181
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    • 1992
  • Tantalum pentoxide($Ta_{2}O_{5}$) thin films on p-type (100) silicon wafer were fabricated by RF reactive sputtering. Physical properties and structure of the specimens were examined by XRD and AES. From the C-V analysis, the dielectric constant of $Ta_{2}O_{5}$ films was in the range of 10-12 in the reactive gas atmosphere in which 10% of oxygen gas is mixed. The ratio of Ta : 0 was 1 : 2 and 1 : 2.49 by AES and RBS examination, respectively. The heat-treatment at $700^{\circ}C$ in $O_{2}$ ambient led to induce crystallization. When the heat-treatment temperature was $1000^{\circ}C$, the dielectric constant was 20.5 in $O_{2}$ ambient and 23 in $N_{2}$ ambient, respectively. The crystal structure of $Ta_{2}O_{5}$ film was pseudo hexagonal of ${\delta}-Ta_{2}O_{5}$. The flat band voltage shift(${\Delta}V_{FB}$) of the specimens and the leakage current density were decreased for higher oxygen mixing ratio. The maximum breakdown field was 2.4MV/cm at the oxygen mixing ratio of 10%. The $Ta_{2}O_{5}$ films will be applicable to hydrogen ion sensitive film and gate oxide material for memory device.

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