• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.8
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• pp.344-349
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• 2017

Wall-climbing robots have been developed for various purposes, such as cleaning skyscraper windows, maintaining large structures, and welding vessels. Conventional wall-climbing robots use movement systems based on wheels or legs. However, wheeled robots suffer from slipping effects, while legged systems require many actuators and control systems for the complex linkage structure, which also increases the weight of the robot. To overcome these disadvantages, we propose a new wall-climbing robot that walks based on gorilla locomotion. The proposed robot consists of a DC drive motor, a vacuum pump for adsorption, and a micro controller for controlling the system. The performance of the robot was experimentally verified on vertical and horizontal flat surfaces. The robot could be used for various functions in industrial sites or disaster areas.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1729-1750
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• 2018

Voltage source inverters (VSIs) are widely used to drive induction motors in industry applications. The quality of output waveforms depends on the switching sequences used in pulse width modulation (PWM). In this work, all existing optimal space vector pulse width modulation (SVPWM) switching strategies are studied. The performance of existing SVPWM switching strategies is optimized to realize a tradeoff between quality of output waveforms and switching losses. This study generalizes the existing optimal switching sequences for total harmonic distortions (THDs) and switching losses for different modulation indexes and reference angles with a parameter called quality factor. This factor provides a common platform in which the THDs and switching losses of different SVPWM techniques can be compared. The optimal spatial distribution of each sequence is derived on the basis of the quality factor to minimize harmonic current distortions and switching losses in a sector; the result is the minimum ripple loss SVPWM (MRSLPWM). By employing the sequences from optimized switching maps, the proposed method can simultaneously reduce THDs and switching losses. Two hybrid SVPWM techniques are proposed to reduce line current distortions and switching losses in motor drives. The proposed hybrid SVPWM strategies are MRSLPWM 30 and MRSLPWM 90. With a low-cost PIC microcontroller (PIC18F452), the proposed hybrid SVPWM techniques and the quality of output waveforms are experimentally validated on a 2 kVA VSI based on a three-phase two-level insulated gate bipolar transistor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.8
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• pp.966-974
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• 2019

In this study, we propose a CMOS power amplifier (PA) using a bypass technique to enhance the efficiency in the low-power region. For the bypass structure, the common-gate (CG) transistor of the cascode structure of the driver stage is divided in two parallel branches. One of the CG transistors is designed to drive the power stage for high-power mode. The other CG transistor is designed to bypass the power stage for low-power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. The measured maximum output power is 20.35 dBm with a power added efficiency of 12.10%. At a measured output power of 11.52 dBm, the PAE is improved from 1.90% to 7.00% by bypassing the power stage. Based on the measurement results, we verified the functionality of the proposed bypass structure.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.2 s.302
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• pp.49-58
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• 2005

A new soft switching three-phase PWM rectifier with simple circuit configuration and high efficiency has been developed. The proposed circuit is a kind of the auxiliary resonant commutated Pole(ARCP)converter The conventional ARCP converter requires three-auxiliary reactors and six-auxiliary switches for the soft switching auxiliary circuit and for these switching elements, a gate drive circuit and a control circuit are required, resulting in high part as a disadvantage. In the main circuit proposed in this paper, the auxiliary soft switching circuit is composed of two-auxiliary reactors, two-auxiliary switches and several diodes. In addition, common use of the PWM control circuit for two-switches will make the control circuit of the auxiliary switches simple. By means of function of the soft switching auxiliary circuit, the main switching element performs zero voltage switching operation and the auxiliary switches perform the zero current switching. In this paper, the circuit configuration and the operational analysis of the proposed circuit are described at first and then, experimental results will be reported. By using a prototype with 5[kW] capacity, the conversion efficiency of maximum $98.8[\%]$ and the power factor of $99[\%]$ or higher were obtained.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.456-456
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• 2010

CMOS 소자가 서브마이크론($0.1\;{\mu}m$) 이하로 스케일다운 되면서 단채널 효과(short channel effect), 게이트 산화막(gate oxide)의 누설전류(leakage current)의 증가와 높은 직렬저항(series resistance) 등의 문제가 발생한다. CMOS 소자의 구동전류(drive current)를 높이고, 단채널 효과를 줄이기 위한 가장 효율적인 방법은 소스 및 드레인의 얕은 접합(shallow junction) 형성과 직렬 저항을 줄이는 것이다. 플라즈마 도핑 방법은 플라즈마 밀도 컨트롤, 주입 바이어스 전압 조절 등을 통해 저 에너지 이온주입법보다 기판 손상 및 표면 결함의 생성을 억제하면서 고농도로 얕은 접합을 형성할 수 있다. 그리고 얕은 접합을 형성하기 위해 주입된 불순물의 활성화와 확산을 위해 후속 열처리 공정은 높은 온도에서 짧은 시간 열처리하여 불순물 물질의 활성화를 높여주면서 열처리로 인한 접합 깊이를 얕게 해야 한다. 그러나 접합의 깊이가 줄어듦에 따라서 소스 및 드레인의 표면 저항(sheet resistance)과 접촉저항(contact resistance)이 급격하게 증가하는 문제점이 있다. 이러한 표면저항과 접촉저항을 줄이기 위한 방안으로 실리사이드 박막(silicide thin film)을 형성하는 방법이 사용되고 있다. 본 논문에서는 (100) p-type 웨이퍼 He(90 %) 가스로 희석된 $PH_3$(10 %) 가스를 사용하여 플라즈마 도핑을 실시하였다. 10 mTorr의 압력에서 200 W RF 파워를 인가하여 플라즈마를 생성하였고 도핑은 바이어스 전압 -1 kV에서 60 초 동안 실시하였다. 얕은 접합을 형성하기 위한 불순물의 활성화는 ArF(193 nm) excimer laser를 통해 $460\;mJ/cm^2$의 에니지로 열처리를 실시하였다. 그리고 낮은 접촉비저항과 표면저항을 얻기 위해 metal sputter를 통해 TiN/Ti를 $800/400\;{\AA}$ 증착하고 metal RTP를 사용하여 실리사이드 형성 온도를 $650{\sim}800^{\circ}C$까지 60 초 동안 열처리를 실시하여 $TiSi_2$ 박막을 형성하였다. 그리고 $TiSi_2$의 두께를 측정하기 위해 TEM(Transmission Electron Microscopy)을 측정하였다. 화학적 결합상태를 분석하기 위해 XPS(X-ray photoelectronic)와 XRD(X-ray diffraction)를 측정하였다. 접촉비저항, 접촉저항과 표면저항을 분석하기 위해 TLM(Transfer Length Method) 패턴을 제작하여 I-V 특성을 측정하였다. TEM 측정결과 $TiSi_2$의 두께는 약 $580{\AA}$ 정도이고 morphology는 안정적이고 실리사이드 집괴 현상은 발견되지 않았다. XPS와 XRD 분석결과 실리사이드 형성 온도가 $700^{\circ}C$에서 C54 형태의 $TiSi_2$ 박막이 형성되었고 가장 낮은 접촉비저항과 접촉저항 값을 가진다.