• Proceedings of the KIEE Conference
• /
• 1994.07a
• /
• pp.573-575
• /
• 1994

Resent research activities and technical trends for UPS(UNINTERRUPTIBLE POWER SUPPLY) are reviewed. There are increasing demands for UPS to get mote useful performance. This needs are high-efficiency, high-confidency, high-quality, low-cost. self-diagnosis. maintenance-free, and a wide variety of options. These can be satisfied with high-technology and optimal system coordination. In this paper. according to these demands. a newly developed UPS and a wide variety of options are introduced. Also. the data related are presented.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.79-79
• /
• 2013

Quantum-structures with nanoparticles have been attractive for various electronic and photonic devices [1,2]. In recent, nonvolatile memories such as nano-floating gate memory (NFGM) and resistance random access memory (ReRAM) have been studied using silicides, metals, and metal oxides nanoparticles [3,4]. In this study, we fabricated nonvolatile memories with silicides (WSi2, Ti2Si, V2Si) and metal-oxide (Cu2O, Fe2O3, ZnO, SnO2, In2O3 and etc.) nanoparticles embedded in polyimide matrix, and photovoltaic device also with SiC nanoparticles. The capacitance-voltageand current-voltage data showed a threshold voltage shift as a function of write/erase voltage, which implies the carrier charging and discharging into the metal-oxide nanoparticles. We have investigated also the electrical properties of ReRAM consisted with the nanoparticles embedded in ZnO, SiO2, polyimide layer on the monolayered graphene. We will discuss what the current bistability of the nanoparticle ReRAM with monolayered graphene, which occurred as a result of fully functional operation of the nonvolatile memory device. A photovoltaic device structure with nanoparticles was fabricated and its optical properties were also studied by photoluminescence and UV-Vis absorption measurements. We will discuss a feasibility of nanoparticles to application of nonvolatile memories and photovoltaic devices.

• International Journal of Aeronautical and Space Sciences
• /
• v.18 no.4
• /
• pp.675-687
• /
• 2017

In the aerospace industry, we have produced various models according to operational conditions and the environment after development of the base model is completed. Therefore, when design change is necessary, there are modification and updating costs of the circuit whenever environment variables change. For these reasons, recently, in various fields, system designs that can flexibly respond to changing environmental conditions using field programmable gate arrays (FPGAs) are attracting attention, and the rapidly changing aerospace industry also uses FPGAs to organize the system environment. In this paper, we design the controller area network (CAN) intellectual property (IP) protocol used instead of the avionics protocol that includes ARINC-429 and MIL-STD-1553, which are not suitable for small unmanned aerial vehicle (UAV) systems at the register transistor logic (RTL) level, which does not depend on the FPGA vender, and we verify the performance. Consequentially, a Spartan 6 FPGA model-based system on chip (SoC) including an embedded system is constructed by using the designed CAN communications IP and Xilinx Microblaze, and the configured SoC only recorded an average 32% logic element usage rate in the Spartan 6 FPGA model.

• Proceedings of the KIEE Conference
• /
• 2006.10c
• /
• pp.388-390
• /
• 2006

This paper presents a hybrid SoC design for phase detection of single tone signal. The designed hybrid SoC is composed of three functional blocks, i.e., an analog to digital converter module, a phase detection module and a controller module. A design of the controller module is based on a 16-bit RISC architecture. An I/O interface and an LCD control interface for transmission and display of phase measurement values are included in the design of the controller module. A design of the phase detector is based on a recursive sliding-DFT. The recursive architecture effectively reduces the gate numbers required in the implementation of the module. The ADC module includes a single-bit second-order sigma-delta modulator and a digital decimation filter. The decimation filter is designed to give 98dB of SNR for the ADC. The effective resolution of the ADC is enhanced to 98dB of SNR by the incorporation of a pre FIR filter, a 2-stage cascaded integrator- comb(CIC) filter and a 30-tab FIR filter in the decimation. The hybrid SoC is verified in FPGA and implemented in 0.35 CMOS Technology.

• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.37 no.5
• /
• pp.93-102
• /
• 2000

This paper describes the architecture and characteristics of the satellite modem unit (SMU) developed for the DAMA-SCPC Ground System(DGS), which is a Demand Assignment Multiple Access-Single Channel per Carrier (DAMA-SCPC) satellite network. There are several requirements for the SMU from the system architecture and design concept. To meet these requirements the SMU was designed and implemented by extensively applying digital signal processing (DSP) technique and field programmable gate array (FPGA). The developed SMU met the functional and performance requirements, and has been working well. The measured BER was about 1 $\times$10E-4 in continuous mode(at Eb/No=4.7, FEC=3/4).

• Journal of the Korean housing association
• /
• v.27 no.3
• /
• pp.23-30
• /
• 2016

Among the unearthed House ruins in Gyeongju of the capital of Silla period, the ruins to see the overall appearance of building arrangement is the ruins of Silla capital S1E1 area, Inwangdong 412, and the Jaemaejeong. In this study, the characteristics of urban house arrangement of the Unified Silla period was analyzed that, through a review of the arrangement relationship between the gate and the individual buildings found in these ruins. The urban house of the Unified Silla period was surrounded with wall, and the way to distinguish between functional areas within it are shown differently, depending on the size of the house. In other words, the small house was divided each area by installation of inner fence, and the large house was by arranging attached buildings. Thai is, the central area is not divided by inner fence is the Characteristics that is different from the small house. And in all houses, a large courtyard is located in the front of main building. Conatruction of the courtyard determines the location and direction of the main building. And the each area has external space of courtyard in the center.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2014.02a
• /
• pp.180.2-180.2
• /
• 2014

Opening a bandgap by forming graphene nanoribbons (GNRs) and tailoring their properties via doping is a promising direction to achieve graphene-based advanced electronic devices. Applying a first-principles computational approach combining density functional theory (DFT) and DFT-based non-equilibrium Green's function (NEGF) calculation, we herein study the structural, electronic, and charge transport properties of boron-nitrogen binary edge doped GNRs and show that it can achieve novel doping effects that are absent for the single B or N doping. For the armchair GNRs, we find that the B-N edge co-doping almost perfectly recovers the conductance of pristine GNRs. For the zigzag GNRs, it is found to support spatially and energetically spin-polarized currents in the absence of magnetic electrodes or external gate fields: The spin-up (spin-down) currents along the B-N undoped edge and in the valence (conduction) band edge region. This may lead to a novel scheme of graphene band engineering and benefit the design of graphene-based spintronic devices.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.08a
• /
• pp.287-287
• /
• 2010

We report a new direct patterning method, called liquid bridge-mediated nanotransfer molding (LB-nTM), for the formation of two- or three-dimensional structures with feature sizes between tens of nanometers and tens of micron over large areas. LB-nTM is based on the direct transfer of various materials from a mold to a substrate via a liquid bridge between them. This procedure can be adopted for automated direct printing machines that generate patterns of functional materials with a wide range of feature sizes on diverse substrates. Arrays of TIPS-PEN TFTs were fabricated on 4" polyethersulfone (PES) substrates by LB-nTM using PDMS molds. An inverted staggered structure was employed in the TFT device fabrication. A 150 nm-thick indium-tin oxide (ITO) gate electrode and a 200 nm-thick SiO2dielectric layer were formed on a PES substrate by sputter deposition. An array of TIPS-PEN patterns (thickness: 60 nm) as active channel layers was fabricated on the substrate by LB-nTM. The nominal channel length of the TIPS-PEN TFT was 10 mm, while the channel width was 135 mm. Finally, the source and drain electrodes of 200 nm-thick Ag were defined on the substrate by LB-nTM. The TIPS-PEN TFTs can endure strenuous bending and are also transparent in the visible range, and therefore potentially useful for flexible and invisible electronics.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.32 no.7
• /
• pp.83-90
• /
• 2004

This paper describes on-board decentralized data acquisition system that acquires and encodes the numerous sensor data distributed on the big flight vehicles efficiently. The system's sub-units which have one encoder unit and several remote units were designed and simulated according to the communication protocols and the control, sequence logics based on the FPGA chip. And we have made the functional verification of the acquisition, collection and formatting of remote analog and digital data for the manufactured hardwares.

• The Journal of the Korea Contents Association
• /
• v.6 no.11
• /
• pp.225-234
• /
• 2006

In this paper, we design a combined security processor, ECC, MD-5, and AES, as a SIP for cryptography of securing contents. Each SIP is modeled and designed in VHDL and implemented as a reusable macro through logic synthesis, simulation and FPGA verification. To communicate with an ARM9 core, we design a BFM(Bus Functional Model) according to AMBA AHB specification. The combined security SIP for a platform-based SoC is implemented by integrating ECC, AES and MD-5 using the design kit including the ARM9 RISC core, one million-gate FPGA. Finally, it is fabricated into a MPW chip using Magna chip $0.25{\mu}m(4.7mm{\times}4.7mm$) CMOS technology.