• Journal of the Korea Society of Computer and Information
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• v.4 no.3
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• pp.73-77
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• 1999

In this paper. wavelet transform coding for image conference is studied. Original video frames are transformed into hierarchical pyramidal images with multiresolution using the band property of wavelet transform coefficients. Moving information between neighboring frames is obtained from the low-resolution band. Also, to control the video coding procedure. a new picture set filter is proposed. This filter controls the compression ratio of each frame depending on the correlation to the reference frame by selectively eliminating less important high-resolution areas. Consequently. video quality can be preserved and bit rate can be controlled adaptively In the simulation, to test the performance of the proposed coding method, comparisons with the full search block matching algorithm and the differential image coding algorithm are made. Consequently. the proposed method shows a reasonably good performance over existing ones.

• Proceedings of the Korea Information Processing Society Conference
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• 2000.04a
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• pp.1112-1115
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• 2000

본 논문에서는 One-bit 변환을 기반으로 한 고속의 가변 블록 크기 움직임 예측 알고리즘을 제안한다. 제안된 방법은 블록 내의 평균값을 이용하여 8bit 화소값을 1bit로 변환한 후 움직임 예측을 수행한다. One-bit 변환을 통한 영상의 단순화는 움직임 추정의 계산적 부담을 감소시켜 빠른 탐색을 가능하게 한다. 그리고 블록 내의 움직임 정도를 미리 판별하여 이를 기반으로 한 적응적 탐색이 불필요한 탐색을 제거하고 움직임이 큰 블록에서는 정합과정을 심화시켜 보다 정확한 움직임 예측을 수행한다. 본 제안된 방식을 가지고 실험한 결과 한 프레임당 적은 수의 블록으로 고정된 크기의 블록을 가진 전역 탐색 블록 정합 알고리즘(full search block matching algorithm; FSBMA)보다 예측 에러를 적게 발생시켜 평균적으로 0.5dB 정도의 PSNR 개선을 가져왔다. 특히, 움직임이 많은 영상에서 뛰어난 효과를 나타냈다.

• Journal of Broadcast Engineering
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• v.16 no.5
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• pp.861-872
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• 2011

Many fast block-matching algorithms (BMAs) in motion estimation field reduce computational complexity by screening the number of checking points. Although many fast BMAs reduce computations, sometimes they should endure matching errors in comparison with full-search algorithm (FSA). In this paper, a novel fast BMA for constrained one-bit transform (C1BT)-based motion estimation is proposed in order to decrease the calculations of the block distortion measure. Unlike the classical fast BMAs, the proposed algorithm shows a new approach to reduce computations. It utilizes the binomial distribution based on the characteristic of binary plane which is composed of only two elements: 0 and 1. Experimental results show that the proposed algorithm keeps its peak signal-to-noise ratio (PSNR) performance very close to the FSA-C1BT while the computation complexity is reduced considerably.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.12
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• pp.5860-5876
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• 2018

A single snapshot data can only provide limited amount of information so that the rank of covariance matrix is not full, which is not adopted to complete the parameter estimation directly using the traditional super-resolution method. Aiming at solving the problem, a joint time delay and angle estimation using matrix pencil method based on information reconstruction vector for orthogonal frequency division multiplexing (OFDM) signal is proposed. Firstly, according to the channel frequency response vector of each array element, the algorithm reconstructs the vector data with delay and angle parameter information from both frequency and space dimensions. Then the enhanced data matrix for the extended array element is constructed, and the parameter vector of time delay and angle is estimated by the two-dimensional matrix pencil (2D MP) algorithm. Finally, the joint estimation of two-dimensional parameters is accomplished by the parameter pairing. The algorithm does not need a pseudo-spectral peak search, and the location of the target can be determined only by a single receiver, which can reduce the overhead of the positioning system. The theoretical analysis and simulation results show that the estimation accuracy of the proposed method in a single snapshot and low signal-to-noise ratio environment is much higher than that of Root Multiple Signal Classification algorithm (Root-MUSIC), and this method also achieves the higher estimation performance and efficiency with lower complexity cost compared to the one-dimensional matrix pencil algorithm.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.943-949
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• 2010

This paper presents some improvements on VLSI implementation of lifting-based 9/7 wavelet transform by optimization hardware multiplication. The proposed solution requires less logic area and power consumption without performance loss compared to previous wavelet filter structure based on lifting scheme. This paper proposes a better approach to the hardware implementation using Lefevre algorithm based on extensions of Pattern search methods. To compare the proposed structure to the previous solutions on full multiplier blocks, we implemented them using Verilog HDL. For a hardware implementation of the two solutions, the logical synthesis on 0.18 um standard cells technology show that area, maximum delay and power consumption of the proposed architecture can be reduced up to 51%, 43% and 30%, respectively, compared to previous solutions for a 200 MHz target clock frequency. Our evaluation show that when design VLSI chip of lifting-based 9/7 wavelet filter, our solution is better suited for standard-cell application-specific integrated circuits than prior works on complete multiplier blocks.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.1
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• pp.23-30
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• 2010

The H.264/AVC is increasingly used in broadcast video applications such as Internet Protocol television (IPTV), digital multimedia broadcasting (DMB) because of high compression performance. But the H.264/AVC coded video can be delivered to the widespread end-user equipment for MPEG-2 after transcoding between this video standards. This paper suggests a new transcoding algorithm for H.264/AVC to MPEG-2 transcoder that uses motion vector clustering in order to reduce the complexity without loss of video quality. The proposed method is exploiting the motion information gathered during h.264 decoding stage. To reduce the search space for the MPEG-2 motion estimation, the predictive motion vector is selected with a least distortion of the candidated motion vectors. These candidate motion vectors are considering the correlation of direction and distance of motion vectors of variable blocks in H.264/AVC. And then the best predictive motion vector is refined with full-search in ${\pm}2$ pixel search area. Compared with a cascaded decoder-encoder, the proposed transcoder achieves computational complexity savings up to 64% with a similar PSNR at the constant bitrate(CBR).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.3C
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• pp.288-296
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• 2009

In POCS (projection onto convex sets)-based reconstruction of HR (high resolution) image, the quality of reconstructed image is gradually improved through iterative motion estimation and image restoration. The amount of computation, however, increases because of the repeated inter-frame motion estimation. In this paper, an HR reconstruction algorithm is proposed where modified ARPS (adaptive rood pattern search) and POCS are simultaneously performed. In the modified ARPS, the motion estimates obtained from phase correlation or from the previous steps in POCS restoration are utilized as the initial reference in the motion estimation. Moreover, estimated motion is regularized with reference to the neighboring blocks' motion to enhance the reliability. Computer simulation results show that, when compared to conventional methods which are composed of full search block matching and POCS restoration, the proposed method is about 30 times faster and yet produces HR images of almost equal or better quality.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4A
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• pp.364-370
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• 2002

In this paper, we propose a VLSI array architecture for high speed processing of FBMA. First of all, the sequential FBMA is transformed into a single assignment code by using the index space expansion, and then the dependance graph is obtained from it. The two dimensional VLSI array is derived by projecting the dependance graph along the optimal direction. Since the candidate blocks in the search range are overlapped with columns as well as rows, the processing elements of the VLSI array are designed to reuse the overlapped data. As the results, the number of data inputs is reduced so that the processing performance is improved. The proposed VLSI array has (N$^2$+1)${\times}$(2p+1) processing elements and (N+2p) input ports where N is the block size and p is the maximum search range. The computation time of the rat reference block is (N$^2$+2(p+1)N+6p), and the block pipeline period is (3N+4p-1).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.58-65
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and variable point 2D SAD hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the SAD unit and its parallel operations using pattern information, the proposed IME instructions support not only full search algorithms but also other fast search algorithms. The hardware size is 25.5K gates for each Processing Element Group (PEG) which has 128 SAD Processor Elements (PEs). The proposed ASIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The hardware size is 453K gates for the IME unit and the operating frequency is 188MHz for 1080p@30 frame in real time. The proposed ASIP can reduce the hardware size about 26% and the number of operation cycles about 18%.

• Journal of Broadcast Engineering
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• v.9 no.4 s.25
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• pp.434-445
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• 2004

Motion Estimation is an essential module in video encoders based on international standards such as H.263 and MPEG. Many fast motion estimation algorithms have been proposed in order to reduce the computational complexity of a well-known full search algorithms(FS). However, these fast algorithms can not work efficiently in DSP processors recently developed for video processing. To solve for this. we propose an efficient motion estimation scheme optimized in the DSP processor like Philips TM1300. A motion vector predictor is pre-estimated and a small search range is chosen in the proposed scheme using strong motion vector correlation between a current macro block (MB) and its neighboring MB's to reduce computation time. An MPEG-4 SP@L3(Simple Profile at Level 3) encoding system is implemented in Philips TM1300 to verify the effectiveness of the proposed method. In that processor, we can achieve better performance using our method than other conventional ones while keeping visual quality as good as that of the FS.